From fc7400093da994e9855cc045f9f8e226f4817e85 Mon Sep 17 00:00:00 2001 From: "Mike J. Chen" Date: Thu, 22 Mar 2012 15:51:03 -0700 Subject: ARMV7: OMAP3: MMC: Enable 8-bit mode for MMC1 and MMC2 controllers MMC0 is the only one limited to 4-bit on OMAP3. Change-Id: I31e922d39e4b23c3cc41f77f50d1ee572cc33364 Signed-off-by: Mike J. Chen --- drivers/mmc/omap_hsmmc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index fbac289a5..b65f72cca 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -734,6 +734,10 @@ int omap_mmc_init(int dev_index) */ if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) mmc->b_max = 1; + + /* MMC1 and MMC2 support 8-bit, but MMC0 only supports 4-bit */ + if (dev_index != 0) + mmc->host_caps |= MMC_MODE_8BIT; #endif mmc_register(mmc); -- cgit v1.2.3 From 10e01499cf44ac7291e89719f4cb11a94f944696 Mon Sep 17 00:00:00 2001 From: "Mike J. Chen" Date: Mon, 26 Mar 2012 15:35:28 -0700 Subject: TWL4030: Force power down before powering up the PHY To address issues with USB not enumerating properly when the cable is connected on a warm reboot, make sure the PHY is powered down before powering it up. This results in proper enumeration on a warm reboot. Change-Id: If52df6386ec7c8bd3c6715b96644e1dad752b9a7 --- drivers/usb/phy/twl4030.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/usb/phy/twl4030.c b/drivers/usb/phy/twl4030.c index 54d2e615c..6dcf6c92e 100644 --- a/drivers/usb/phy/twl4030.c +++ b/drivers/usb/phy/twl4030.c @@ -118,10 +118,22 @@ static void twl4030_phy_power(void) { u8 pwr, clk; - /* Power the PHY */ + /* First make sure PHY is powered down to + * clear any state from a previous reboot and + * force unenumeration. Otherwise, sometimes + * the device doesn't enumerate properly on + * a warm reboot. + */ + + /* Power down the PHY */ pwr = twl4030_usb_read(TWL4030_USB_PHY_PWR_CTRL); + pwr |= PHYPWD; + twl4030_usb_write(TWL4030_USB_PHY_PWR_CTRL, pwr); + + /* Power the PHY */ pwr &= ~PHYPWD; twl4030_usb_write(TWL4030_USB_PHY_PWR_CTRL, pwr); + /* Enable clocks */ clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); clk |= CLOCKGATING_EN | CLK32K_EN; @@ -139,6 +151,8 @@ int twl4030_usb_ulpi_init(void) long timeout = 1000 * 1000; /* 1 sec */; u8 clk, sts, pwr; + i2c_set_bus_num(0); + /* twl4030 ldo init */ twl4030_usb_ldo_init(); -- cgit v1.2.3 From c0eec2d5698a6722a195f4545064dccfb4010c16 Mon Sep 17 00:00:00 2001 From: "Mike J. Chen" Date: Fri, 30 Mar 2012 09:37:05 -0700 Subject: OMAP4+: Correct the dpll lock sequence The recommended sequence to update the frequencies for different dplls are core, mpu, iva. Currently though core dpll is configured first locking is done only with the emif freq update mechanism. So the sequence is mpu, core. Change this so that the core dpll is locked first and only the post dividers are changed by freq update procedure later. Change-Id: I06a7fccd3e33905193d1c24b62e6b1e1ac8e44ef Signed-off-by: R Sricharan Signed-off-by: Mike J. Chen --- arch/arm/cpu/armv7/omap4/clocks.c | 26 ++++++++++++++++++++------ arch/arm/cpu/armv7/omap4/emif.c | 4 ---- arch/arm/include/asm/arch-omap4/emif.h | 6 ++++++ 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index c8777580e..7c58b9f6d 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -36,6 +36,7 @@ #include #include #include +#include #ifndef CONFIG_OMAP4430_ES1_0_MPU_DPLL #define CONFIG_OMAP4430_ES1_0_MPU_DPLL mpu_dpll_params_1200mhz @@ -425,6 +426,13 @@ void configure_mpu_dpll(void) debug("MPU DPLL locked\n"); } +static void init_m2_core_dpll(u32 *const base, int m2) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + writel(m2, &dpll_regs->cm_div_m2_dpll); +} + static void setup_dplls(void) { u32 sysclk_ind, temp; @@ -435,12 +443,17 @@ static void setup_dplls(void) /* CORE dpll */ params = get_core_dpll_params(); /* default - safest */ + /* - * Do not lock the core DPLL now. Just set it up. - * Core DPLL will be locked after setting up EMIF - * using the FREQ_UPDATE method(freq_update_core()) + * Lock the core DPLL here to get the right sequence. + * But set the M2 post divider to a maximum value so that + * emif/ddr freqeuncy is at a low value for the beginning. + * FREQ_UPDATE method(freq_update_core()) updates the correct + * m2 later. */ - do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK); + do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_LOCK); + init_m2_core_dpll(&prcm->cm_clkmode_dpll_core, CORE_DPLL_M2_INIT); + /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | @@ -448,13 +461,14 @@ static void setup_dplls(void) writel(temp, &prcm->cm_clksel_core); debug("Core DPLL configured\n"); + /* MPU dpll */ + configure_mpu_dpll(); + /* lock PER dpll */ do_setup_dpll(&prcm->cm_clkmode_dpll_per, &per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK); debug("PER DPLL locked\n"); - /* MPU dpll */ - configure_mpu_dpll(); } static void setup_non_essential_dplls(void) diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c index 45c88aba8..77fcc2029 100644 --- a/arch/arm/cpu/armv7/omap4/emif.c +++ b/arch/arm/cpu/armv7/omap4/emif.c @@ -1230,10 +1230,6 @@ void sdram_init(void) in_sdram = running_from_sdram(); debug("in_sdram = %d\n", in_sdram); - if (!in_sdram) { - bypass_dpll(&prcm->cm_clkmode_dpll_core); - } - do_sdram_init(OMAP44XX_EMIF1); do_sdram_init(OMAP44XX_EMIF2); diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h index 3a549bad5..35a7a4d5c 100644 --- a/arch/arm/include/asm/arch-omap4/emif.h +++ b/arch/arm/include/asm/arch-omap4/emif.h @@ -907,6 +907,12 @@ struct dmm_lisa_map_regs { #define MR8_IO_WIDTH_SHIFT 0x6 #define MR8_IO_WIDTH_MASK (0x3 << 0x6) +/* + * CORE DPLL m2 divider init, set to maximum + * to have the lowest possible frequency. + */ +#define CORE_DPLL_M2_INIT 0x1F + struct lpddr2_addressing { u8 num_banks; u8 t_REFI_us_x10; -- cgit v1.2.3 From 11c8c96d1cb9f1afef03ff496880945ada7c3d62 Mon Sep 17 00:00:00 2001 From: "Mike J. Chen" Date: Fri, 30 Mar 2012 10:10:13 -0700 Subject: OMAP4: Correct the frequency settings The max dpll lock frequencies for CORE, MPU, IVA domains are set for OPP_NOM. But these are slightly changed as per the latest operating condition addendum V0.4 for 4460 and V0.7 for 4430. Updating this here. Change-Id: I44b8daa83821035b9392c01f749b60a9b357e7a7 Signed-off-by: R Sricharan Signed-off-by: Mike J. Chen --- arch/arm/cpu/armv7/omap4/clocks.c | 82 ++++++++++++++++++--------------------- 1 file changed, 38 insertions(+), 44 deletions(-) diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 7c58b9f6d..ae91fc1e0 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -38,14 +38,11 @@ #include #include -#ifndef CONFIG_OMAP4430_ES1_0_MPU_DPLL -#define CONFIG_OMAP4430_ES1_0_MPU_DPLL mpu_dpll_params_1200mhz -#endif -#ifndef CONFIG_OMAP4430_non_ES1_0_MPU_DPLL -#define CONFIG_OMAP4430_non_ES1_0_MPU_DPLL mpu_dpll_params_1584mhz +#ifndef CONFIG_OMAP4430_MPU_DPLL +#define CONFIG_OMAP4430_MPU_DPLL mpu_dpll_params_1200mhz #endif #ifndef CONFIG_OMAP4460_MPU_DPLL -#define CONFIG_OMAP4460_MPU_DPLL mpu_dpll_params_1840mhz +#define CONFIG_OMAP4460_MPU_DPLL mpu_dpll_params_1400mhz #endif #define str(s) #s @@ -86,15 +83,15 @@ static const u32 sys_clk_array[8] = { * Please use this tool for creating the table for any new frequency. */ -/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */ -static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = { - {230, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {920, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {219, 3, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {575, 11, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {460, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {920, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {575, 23, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */ +static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { + {175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ }; /* dpll locked at 700 MHz MPU clk at 350 MHz(OPP50 4460) - DCC OFF */ @@ -131,34 +128,34 @@ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { }; static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { - {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ - {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ - {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ - {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ - {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ - {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ - {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ + {200, 2, 1, 5, 8, 4, 6, 6}, /* 12 MHz */ + {800, 12, 1, 5, 8, 4, 6, 6}, /* 13 MHz */ + {619, 12, 1, 5, 8, 4, 6, 6}, /* 16.8 MHz */ + {125, 2, 1, 5, 8, 4, 6, 6}, /* 19.2 MHz */ + {400, 12, 1, 5, 8, 4, 6, 6}, /* 26 MHz */ + {800, 26, 1, 5, 8, 4, 6, 6}, /* 27 MHz */ + {125, 5, 1, 5, 8, 4, 6, 6} /* 38.4 MHz */ }; static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { - {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ - {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ - {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ - {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ - {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ - {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ - {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ + {127, 1, 1, 5, 8, 4, 6, 6}, /* 12 MHz */ + {762, 12, 1, 5, 8, 4, 6, 6}, /* 13 MHz */ + {635, 13, 1, 5, 8, 4, 6, 6}, /* 16.8 MHz */ + {635, 15, 1, 5, 8, 4, 6, 6}, /* 19.2 MHz */ + {381, 12, 1, 5, 8, 4, 6, 6}, /* 26 MHz */ + {254, 8, 1, 5, 8, 4, 6, 6}, /* 27 MHz */ + {496, 24, 1, 5, 8, 4, 6, 6} /* 38.4 MHz */ }; static const struct dpll_params core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { - {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */ - {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */ - {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */ - {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */ - {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */ - {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */ - {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */ + {200, 2, 2, 5, 8, 4, 6, 6}, /* 12 MHz */ + {800, 12, 2, 5, 8, 4, 6, 6}, /* 13 MHz */ + {619, 12, 2, 5, 8, 4, 6, 6}, /* 16.8 MHz */ + {125, 2, 2, 5, 8, 4, 6, 6}, /* 19.2 MHz */ + {400, 12, 2, 5, 8, 4, 6, 6}, /* 26 MHz */ + {800, 26, 2, 5, 8, 4, 6, 6}, /* 27 MHz */ + {125, 5, 2, 5, 8, 4, 6, 6} /* 38.4 MHz */ }; static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { @@ -382,10 +379,10 @@ static void print_current_freq(u32 *const base) /* * Lock MPU dpll * - * Resulting MPU frequencies: + * Resulting MPU frequencies (OPP_NUM): * 4430 ES1.0 : 600 MHz - * 4430 ES2.x : 792 MHz (OPP Turbo) - * 4460 : 920 MHz (OPP Turbo) - DCC disabled + * 4430 ES2.x : 600 MHz + * 4460 : 700 MHz */ void configure_mpu_dpll(void) { @@ -396,11 +393,8 @@ void configure_mpu_dpll(void) omap4_rev = omap_revision(); sysclk_ind = get_sys_clk_index(); - if (omap4_rev == OMAP4430_ES1_0) - SET_MPU_DPLL_PARAMS(params, CONFIG_OMAP4430_ES1_0_MPU_DPLL, - sysclk_ind); - else if (omap4_rev < OMAP4460_ES1_0) - SET_MPU_DPLL_PARAMS(params, CONFIG_OMAP4430_non_ES1_0_MPU_DPLL, + if (omap4_rev < OMAP4460_ES1_0) + SET_MPU_DPLL_PARAMS(params, CONFIG_OMAP4430_MPU_DPLL, sysclk_ind); else SET_MPU_DPLL_PARAMS(params, CONFIG_OMAP4460_MPU_DPLL, -- cgit v1.2.3