Age | Commit message (Collapse) | Author |
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am: 2afd8f04b3
am: 090aac9db6
Change-Id: I61511d9c7825ae39e206d7410e5ca9f0f0259472
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am: 2afd8f04b3
Change-Id: I6476ff0764e976ce4b3a684c1ea0ff3d702fb09c
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am: 8608ac5262
Change-Id: I874c82fd658d72570256f5d00766689d741bd95c
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Change-Id: I37e6b218f2745a4432645bbff43899d954c19e41
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Hikey960: Fix hikey960 pcie mount fail
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Set IOC_AO_IOMG_033 function from GPIO213 to PCIE_CLKREQ_N
bit[0-2]: 000: GPIO_213;
001: PCIE_CLKREQ_N;
010: GPIO_018_SH;
100: GPIO_014_SE;
110: FAC_TEST24;
111: FAC_TEST24;
bit[3-31]: reserved
Signed-off-by: Guangtao Zhang <zhangguangtao@hisilicon.com>
Tested-by: Yao Chen <chenyao11@huawei.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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am: 07f5202bf4
Change-Id: I4c571d47fce5087cc0bf958bf278342c9df85d53
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Change-Id: I34e501c7c9839020e53047fec7470c8aec9c7e44
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Change-Id: Ieed88b8053ca3e7249dee5fa8afe4549d39635f1
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am: 72a61be33b
am: f80b69635a
Change-Id: I121dedc746e6db36c8e25fa019aa5f10c3ee22f6
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am: 72a61be33b
Change-Id: I166618ba5d78485718f29d2e74fea65155d92949
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am: d7f137ecb7
Change-Id: I73ec8feea370c133e2da915ac14b8631396eea26
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Change-Id: Ic77734daa3ba792cf235d52b49250a197de4328a
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Update armtf branch AOSP uses to upstream armtf code
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Avoid use of undefined macros
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Change sizeof to use type of struct not function
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qemu: update deprecated interrupt registering
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Enable GICv3 save for ARM platforms
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Registered interrupts are configured in edge detection as the default
previous configuration assumed in previous code.
Not target mask required as Qemu BL31 will not send/route SGIs.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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aarch64: Add PubSub events to capture security state transitions
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These macros are only defined for corresponding image,
and they are undefined for other images. It means that we have
to use ifdef or defined() instead of relying on being 0 by default.
Change-Id: Iad11efab9830ddf471599b46286e1c56581ef5a7
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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ARM_TSP_RAM_LOCATION_ID was defined only in AARCH64, but the macro
was also used in AARCH32, and it meant that it was taking the value 0,
which happened to equal ARM_TRUSTED_SRAM_ID.
Change-Id: If9f4dbee1a2ba15e7806f2a03305b554bd327363
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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debug.S was using macros defined in debug.h, but since it didn't
include it, these macros were taking the value 0, which means that
all the preprocessor conditionals were wrong.
Change-Id: If4ca81cc5a1662991589f914a2557ceff0eaaede
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Add FWU booting instructions to the user guide
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Add platform hooks for boot redundancy support
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Change sizeof call so it references a static type instead of return of
a function in order to be MISRA compliant.
Change-Id: I6f1adb206073d6cd200156e281b8d76249e3af0e
Signed-off-by: Joel Hutton <joel.hutton@arm.com>
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Add events that trigger before entry to normal/secure world. The
events trigger after the normal/secure context has been restored.
Similarly add events that trigger after leaving normal/secure world.
The events trigger after the normal/secure context has been saved.
Change-Id: I1b48a7ea005d56b1f25e2b5313d77e67d2f02bc5
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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FWU uses additional images that have to be loaded,
and this patch adds the documentation of how to do
it in FVP and Juno.
Change-Id: I1a40641c11c5a4c8db0aadeaeb2bec30c9279e28
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Big transition to upstream ARMTF code.
This merges the aosp/mater code with fd3bba4bd523 but merges
such that the tree should be identical with the fd3bba4bd523
side of the merge.
Change-Id: Ib416a13ce19c6c26fb62c38ccc6fdfbbdf9c4304
Signed-off-by: John Stultz <john.stultz@linaro.org>
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Change the default option of ARM_TSP_RAM_LOCATION and Enlarge the BL2 size on ARM platforms
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So for some reason, when building with the android toolchain,
the hikey ddr initialization code gets stuck.
Adding a NOTICE message here avoids it, which basically tells me
something is broken (possibly the toolchain reordering operations,
or some other memory barrier type issue).
But here we are.
Change-Id: I712c3e4463601def012e51120189fd142311ffd1
Signed-off-by: John Stultz <john.stultz@linaro.org>
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Avoid build issues with the Android toolchain
Change-Id: I2b3f7b7e250d71dafc92eec1ffb279127888e521
Signed-off-by: John Stultz <john.stultz@linaro.org>
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qemu/optee: load OP-TEE pageable part 2MB above OP-TEE image
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qemu: fix holding pen mailbox sequence
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OP-TEE dedicates the end of the Qemu secure DRAM as specific out-of-TEE
secure RAM. To support this configuration the trusted firmware should
not load OP-TEE resources in this area.
To overcome the issue, OP-TEE pageable image is now loaded 2MByte above
the secure RAM base address.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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qemu: Add support for Trusted Board Boot
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This patch adds support for TBB to qemu. An RSA ROT keypair is generated at
build time and is included into BL1/BL2. The key and content certificates
are read over semihosting.
Fixes ARM-software/tf-issues#526
Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
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For Trusted Board Boot, BL2 needs more space to support the ECDSA
and ECDSA+RSA algorithms.
Change-Id: Ie7eda9a1315ce836dbc6d18d6588f8d17891a92d
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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On Arm standard platforms, it runs out of SRAM space when TBB is
enabled, so the TSP default location is changed to dram when TBB
is enabled.
Change-Id: I516687013ad436ef454d2055d4e6fce06e467044
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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These hooks are intended to allow one platform to try load
images from alternative places. There is a hook to initialize
the sequence of boot locations and a hook to pass to the next
sequence.
Change-Id: Ia0f84c415208dc4fa4f9d060d58476db23efa5b2
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Before this change, plat_secondary_cold_boot_setup reads wake up mailbox
as a byte array but through 64bit accesses on unaligned 64bit addresses.
In the other hand qemu_pwr_domain_on wakes secondary cores by writing
into a 64bit array.
This change forces the 64bit mailbox format as PLAT_QEMU_HOLD_ENTRY_SIZE
explicitly specifies it.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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Fix edmac
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Publish and Subscribe framework
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This allows other EL3 components to subscribe to CPU on events.
Update Firmware Design guide to list psci_cpu_on_finish as an available
event.
Change-Id: Ida774afe0f9cdce4021933fcc33a9527ba7aaae2
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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This light-weight framework enables some EL3 components to publish
events which other EL3 components can subscribe to. Publisher can
optionally pass opaque data for subscribers. The order in which
subscribers are called is not defined.
Firmware design updated.
Change-Id: I24a3a70b2b1dedcb1f73cf48313818aebf75ebb6
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Migrate upstream platforms to using interrupt properties
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New GIC APIs and specifying interrupt propertes
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fiptool: Enable Visual Studio build
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Add APIs to get and modify attributes of memory regions
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