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| author | Etienne Carriere <etienne.carriere@linaro.org> | 2017-10-24 01:09:52 +0200 |
|---|---|---|
| committer | Etienne Carriere <etienne.carriere@linaro.org> | 2017-10-24 13:57:36 +0200 |
| commit | 33dd33f8f0ce347209adae1044291e037ab2a0e1 (patch) | |
| tree | bbf4f4b3db9545478a5002d101c06c4f39c36e78 | |
| parent | 3b39efa49d9949c80b6e76b99829f84619b46110 (diff) | |
| download | arm-trusted-firmware-33dd33f8f0ce347209adae1044291e037ab2a0e1.tar.gz | |
qemu: fix holding pen mailbox sequence
Before this change, plat_secondary_cold_boot_setup reads wake up mailbox
as a byte array but through 64bit accesses on unaligned 64bit addresses.
In the other hand qemu_pwr_domain_on wakes secondary cores by writing
into a 64bit array.
This change forces the 64bit mailbox format as PLAT_QEMU_HOLD_ENTRY_SIZE
explicitly specifies it.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
| -rw-r--r-- | plat/qemu/aarch64/plat_helpers.S | 1 | ||||
| -rw-r--r-- | plat/qemu/include/platform_def.h | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/plat/qemu/aarch64/plat_helpers.S b/plat/qemu/aarch64/plat_helpers.S index f287e5b5..ed553795 100644 --- a/plat/qemu/aarch64/plat_helpers.S +++ b/plat/qemu/aarch64/plat_helpers.S @@ -63,6 +63,7 @@ endfunc plat_is_my_cpu_primary func plat_secondary_cold_boot_setup /* Calculate address of our hold entry */ bl plat_my_core_pos + lsl x0, x0, #PLAT_QEMU_HOLD_ENTRY_SHIFT mov_imm x2, PLAT_QEMU_HOLD_BASE /* Wait until we have a go */ diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h index e91a7db9..9b5eba37 100644 --- a/plat/qemu/include/platform_def.h +++ b/plat/qemu/include/platform_def.h @@ -90,7 +90,8 @@ #define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) #define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ PLAT_QEMU_HOLD_ENTRY_SIZE) -#define PLAT_QEMU_HOLD_ENTRY_SIZE 8 +#define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 +#define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) #define PLAT_QEMU_HOLD_STATE_WAIT 0 #define PLAT_QEMU_HOLD_STATE_GO 1 |