From df12473802c39c93ab648c9fd958ecdd13760ae4 Mon Sep 17 00:00:00 2001 From: Li Wei Date: Thu, 25 Jan 2018 20:51:27 +0800 Subject: hynix ufs have some bugs for fixed --- Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c | 12 +++++++++++- Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.h | 5 ++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c index 562218e..3fac2d3 100644 --- a/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c +++ b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c @@ -508,13 +508,23 @@ UfsHcPhyInit ( EFI_STATUS EFIAPI UfsHcPhySetPowerMode ( - IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This + IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This, + IN UINT32 DevQuirks ) { UFS_HOST_CONTROLLER_PRIVATE_DATA *Private; UINT32 Data, TxLanes, RxLanes; Private = UFS_HOST_CONTROLLER_PRIVATE_DATA_FROM_UFSHC (This); + + if (DevQuirks & UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME) { + DEBUG ((DEBUG_INFO | DEBUG_LOAD, "ufs: H**** device must set VS_DebugSaveConfigTime 0x10\n")); + /* VS_DebugSaveConfigTime */ + DwUfsDmeSet (Private->RegBase, 0xD0A0, 0x0, 0x10); + /* sync length */ + DwUfsDmeSet (Private->RegBase, 0x1556, 0x0, 0x48); + } + // PA_Tactive DwUfsDmeGet (Private->RegBase, 0x15A8, 0, &Data); if (Data < 7) { diff --git a/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.h b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.h index 8c8476c..6c2fe34 100644 --- a/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.h +++ b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.h @@ -113,6 +113,8 @@ extern EFI_DRIVER_BINDING_PROTOCOL gUfsHcDriverBinding; extern EFI_COMPONENT_NAME_PROTOCOL gUfsHcComponentName; extern EFI_COMPONENT_NAME2_PROTOCOL gUfsHcComponentName2; +#define UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME (1 << 0) + // // Unique signature for private data structure. // @@ -591,6 +593,7 @@ UfsHcPhyInit ( EFI_STATUS EFIAPI UfsHcPhySetPowerMode ( - IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This + IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This, + IN UINT32 DevQuirks ); #endif /* _DW_UFS_HOST_CONTROLLER_H_ */ -- cgit v1.2.3 From 8df412caabdec0b407a82d0937759e5d18ee2e84 Mon Sep 17 00:00:00 2001 From: Riku Voipio Date: Wed, 24 Jan 2018 14:08:20 +0200 Subject: Add device tree files from linux-next (v4.16) --- Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dtb | Bin 0 -> 32130 bytes Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dts | 599 ++++++++ Platforms/Hisilicon/DeviceTree/hi3660.dtsi | 1002 +++++++++++++ .../Hisilicon/DeviceTree/hi3798cv200-poplar.dtb | Bin 0 -> 8882 bytes .../Hisilicon/DeviceTree/hi3798cv200-poplar.dts | 168 +++ Platforms/Hisilicon/DeviceTree/hi3798cv200.dtsi | 423 ++++++ .../Hisilicon/DeviceTree/hi6220-coresight.dtsi | 381 +++++ Platforms/Hisilicon/DeviceTree/hi6220-hikey.dtb | Bin 0 -> 37925 bytes Platforms/Hisilicon/DeviceTree/hi6220-hikey.dts | 548 +++++++ Platforms/Hisilicon/DeviceTree/hi6220.dtsi | 991 +++++++++++++ Platforms/Hisilicon/DeviceTree/hikey-pinctrl.dtsi | 706 +++++++++ .../Hisilicon/DeviceTree/hikey960-pinctrl.dtsi | 1060 +++++++++++++ Platforms/Hisilicon/DeviceTree/hip05-d02.dtb | Bin 0 -> 7035 bytes Platforms/Hisilicon/DeviceTree/hip05-d02.dts | 88 ++ Platforms/Hisilicon/DeviceTree/hip05.dtsi | 369 +++++ Platforms/Hisilicon/DeviceTree/hip06-d03.dtb | Bin 0 -> 15226 bytes Platforms/Hisilicon/DeviceTree/hip06-d03.dts | 54 + Platforms/Hisilicon/DeviceTree/hip06.dtsi | 681 +++++++++ Platforms/Hisilicon/DeviceTree/hip07-d05.dtb | Bin 0 -> 29415 bytes Platforms/Hisilicon/DeviceTree/hip07-d05.dts | 90 ++ Platforms/Hisilicon/DeviceTree/hip07.dtsi | 1560 ++++++++++++++++++++ 21 files changed, 8720 insertions(+) create mode 100644 Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dtb create mode 100644 Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dts create mode 100644 Platforms/Hisilicon/DeviceTree/hi3660.dtsi create mode 100644 Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dtb create mode 100644 Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dts create mode 100644 Platforms/Hisilicon/DeviceTree/hi3798cv200.dtsi create mode 100644 Platforms/Hisilicon/DeviceTree/hi6220-coresight.dtsi create mode 100644 Platforms/Hisilicon/DeviceTree/hi6220-hikey.dtb create mode 100644 Platforms/Hisilicon/DeviceTree/hi6220-hikey.dts create mode 100644 Platforms/Hisilicon/DeviceTree/hi6220.dtsi create mode 100644 Platforms/Hisilicon/DeviceTree/hikey-pinctrl.dtsi create mode 100644 Platforms/Hisilicon/DeviceTree/hikey960-pinctrl.dtsi create mode 100644 Platforms/Hisilicon/DeviceTree/hip05-d02.dtb create mode 100644 Platforms/Hisilicon/DeviceTree/hip05-d02.dts create mode 100644 Platforms/Hisilicon/DeviceTree/hip05.dtsi create mode 100644 Platforms/Hisilicon/DeviceTree/hip06-d03.dtb create mode 100644 Platforms/Hisilicon/DeviceTree/hip06-d03.dts create mode 100644 Platforms/Hisilicon/DeviceTree/hip06.dtsi create mode 100644 Platforms/Hisilicon/DeviceTree/hip07-d05.dtb create mode 100644 Platforms/Hisilicon/DeviceTree/hip07-d05.dts create mode 100644 Platforms/Hisilicon/DeviceTree/hip07.dtsi diff --git a/Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dtb b/Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dtb new file mode 100644 index 0000000..5ccaf0b Binary files /dev/null and b/Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dtb differ diff --git a/Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dts b/Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dts new file mode 100644 index 0000000..c699962 --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dts @@ -0,0 +1,599 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Hisilicon HiKey960 Development Board + * + * Copyright (C) 2016, Hisilicon Ltd. + * + */ + +/dts-v1/; + +#include "hi3660.dtsi" +#include "hikey960-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "HiKey960"; + compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; + + aliases { + mshc1 = &dwmmc1; + mshc2 = &dwmmc2; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + }; + + chosen { + stdout-path = "serial6:115200n8"; + }; + + memory@0 { + device_type = "memory"; + /* rewrite this at bootloader */ + reg = <0x0 0x0 0x0 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@32000000 { + compatible = "ramoops"; + reg = <0x0 0x32000000 0x0 0x00100000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; + }; + }; + + reboot-mode-syscon@32100000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x32100000 0x0 0x00001000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x0>; + + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>; + + power { + wakeup-source; + gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led1 { + label = "user_led1"; + /* gpio_150_user_led1 */ + gpios = <&gpio18 6 0>; + linux,default-trigger = "heartbeat"; + }; + + user_led2 { + label = "user_led2"; + /* gpio_151_user_led2 */ + gpios = <&gpio18 7 0>; + linux,default-trigger = "mmc0"; + }; + + user_led3 { + label = "user_led3"; + /* gpio_189_user_led3 */ + gpios = <&gpio23 5 0>; + default-state = "off"; + }; + + user_led4 { + label = "user_led4"; + /* gpio_190_user_led4 */ + gpios = <&gpio23 6 0>; + panic-indicator; + linux,default-trigger = "cpu0"; + }; + + wlan_active_led { + label = "wifi_active"; + /* gpio_205_wifi_active */ + gpios = <&gpio25 5 0>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt_active_led { + label = "bt_active"; + gpios = <&gpio25 7 0>; + /* gpio_207_user_led1 */ + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; + + pmic: pmic@fff34000 { + compatible = "hisilicon,hi6421v530-pmic"; + reg = <0x0 0xfff34000 0x0 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + ldo3: LDO3 { /* HDMI */ + regulator-name = "VOUT3_1V85"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo9: LDO9 { /* SDCARD I/O */ + regulator-name = "VOUT9_1V8_2V95"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <240>; + }; + + ldo11: LDO11 { /* Low Speed Connector */ + regulator-name = "VOUT11_1V8_2V95"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <240>; + }; + + ldo15: LDO15 { /* UFS VCC */ + regulator-name = "VOUT15_3V0"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + regulator-enable-ramp-delay = <120>; + }; + + ldo16: LDO16 { /* SD VDD */ + regulator-name = "VOUT16_2V95"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <360>; + }; + }; + }; + + wlan_en: wlan-en-1-8v { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + /* GPIO_051_WIFI_EN */ + gpio = <&gpio6 3 0>; + + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +/* + * Legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * "" = no idea, schematic doesn't say, could be + * unrouted (not connected to any external pin) + * LSEC = Low Speed External Connector + * HSEC = High Speed External Connector + * + * Line names are taken from "HiKey 960 Board ver A" schematics + * from Huawei. The 40 pin low speed expansion connector is named + * J2002 63453-140LF. + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART3. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ +&gpio0 { + /* GPIO_000-GPIO_007 */ + gpio-line-names = + "", + "TP901", /* TEST_MODE connected to TP901 */ + "[PMU0_SSI]", + "[PMU1_SSI]", + "[PMU2_SSI]", + "[PMU0_CLKOUT]", + "[JTAG_TCK]", + "[JTAG_TMS]"; +}; + +&gpio1 { + /* GPIO_008-GPIO_015 */ + gpio-line-names = + "[JTAG_TRST_N]", + "[JTAG_TDI]", + "[JTAG_TDO]", + "NC", "NC", + "[I2C3_SCL]", + "[I2C3_SDA]", + "NC"; +}; + +&gpio2 { + /* GPIO_016-GPIO_023 */ + gpio-line-names = + "NC", "NC", "NC", + "GPIO-J", /* LSEC pin 32: GPIO_019 */ + "GPIO_020_HDMI_SEL", + "GPIO-L", /* LSEC pin 34: GPIO_021 */ + "GPIO_022_UFSBUCK_INT_N", + "GPIO-G"; /* LSEC pin 29: LCD_TE0 */ +}; + +&gpio3 { + /* GPIO_024-GPIO_031 */ + /* The rail from pin BK36 is named LCD_TE0, we assume to be muxed as GPIO for GPIO-G */ + gpio-line-names = + "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */ + "[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */ + "NC", + "[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */ + "[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */ + "[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */ + "[I2C3_SDA]", /* HSEC pin 38: ISP_SDA1 */ + "NC"; +}; + +&gpio4 { + /* GPIO_032-GPIO_039 */ + gpio-line-names = + "NC", "NC", + "PWR_BTN_N", /* LSEC pin 4: GPIO_034_PWRON_DET */ + "GPIO_035_PMU2_EN", + "GPIO_036_USB_HUB_RESET", + "NC", "NC", "NC"; +}; + +&gpio5 { + /* GPIO_040-GPIO_047 */ + gpio-line-names = + "GPIO-H", /* LSEC pin 30: GPIO_040_LCD_RST_N */ + "GPIO_041_HDMI_PD", + "TP904", /* Test point */ + "TP905", /* Test point */ + "NC", "NC", + "GPIO_046_HUB_VDD33_EN", + "GPIO_047_PMU1_EN"; +}; + +&gpio6 { + /* GPIO_048-GPIO_055 */ + gpio-line-names = + "NC", "NC", "NC", + "GPIO_051_WIFI_EN", + "GPIO-I", /* LSEC pin 31: GPIO_052_CAM0_RST_N */ + /* + * These two pins should be used for SD(IO) data according to the + * 96boards specification but seems to be repurposed for a IRDA UART. + * They are however named according to the spec. + */ + "[SD_DAT1]", /* HSEC pin 3: UART0_IRDA_RXD */ + "[SD_DAT2]", /* HSEC pin 5: UART0_IRDA_TXD */ + "[UART1_RXD]"; /* LSEC pin 13: DEBUG_UART6_RXD */ +}; + +&gpio7 { + /* GPIO_056-GPIO_063 */ + gpio-line-names = + "[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */ + "[UART0_CTS]", /* LSEC pin 3: UART3_CTS_N */ + "[UART0_RTS]", /* LSEC pin 9: UART3_RTS_N */ + "[UART0_RXD]", /* LSEC pin 7: UART3_RXD */ + "[UART0_TXD]", /* LSEC pin 5: UART3_TXD */ + "[SOC_BT_UART4_CTS_N]", + "[SOC_BT_UART4_RTS_N]", + "[SOC_BT_UART4_RXD]"; +}; + +&gpio8 { + /* GPIO_064-GPIO_071 */ + gpio-line-names = + "[SOC_BT_UART4_TXD]", + "NC", + "[PMU_HKADC_SSI]", + "NC", + "GPIO_068_SEL", + "NC", "NC", "NC"; + +}; + +&gpio9 { + /* GPIO_072-GPIO_079 */ + gpio-line-names = + "NC", "NC", "NC", + "GPIO-K", /* LSEC pin 33: GPIO_075_CAM1_RST_N */ + "NC", "NC", "NC", "NC"; +}; + +&gpio10 { + /* GPIO_080-GPIO_087 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio11 { + /* GPIO_088-GPIO_095 */ + gpio-line-names = + "NC", + "[PCIE_PERST_N]", + "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio12 { + /* GPIO_096-GPIO_103 */ + gpio-line-names = "NC", "NC", "NC", "", "", "", "", "NC"; +}; + +&gpio13 { + /* GPIO_104-GPIO_111 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio14 { + /* GPIO_112-GPIO_119 */ + gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; +}; + +&gpio15 { + /* GPIO_120-GPIO_127 */ + gpio-line-names = + "NC", "NC", "NC", "NC", "NC", "NC", + "GPIO_126_BT_EN", + "TP902"; /* GPIO_127_JTAG_SEL0 */ +}; + +&gpio16 { + /* GPIO_128-GPIO_135 */ + gpio-line-names = "", "", "", "", "", "", "", ""; +}; + +&gpio17 { + /* GPIO_136-GPIO_143 */ + gpio-line-names = "", "", "", "", "", "", "", ""; +}; + +&gpio18 { + /* GPIO_144-GPIO_151 */ + gpio-line-names = + "[UFS_REF_CLK]", + "[UFS_RST_N]", + "[SPI1_SCLK]", /* HSEC pin 9: GPIO_146_SPI3_CLK */ + "[SPI1_DIN]", /* HSEC pin 11: GPIO_147_SPI3_DI */ + "[SPI1_DOUT]", /* HSEC pin 1: GPIO_148_SPI3_DO */ + "[SPI1_CS]", /* HSEC pin 7: GPIO_149_SPI3_CS0_N */ + "GPIO_150_USER_LED1", + "GPIO_151_USER_LED2"; +}; + +&gpio19 { + /* GPIO_152-GPIO_159 */ + gpio-line-names = "NC", "NC", "NC", "NC", "", "", "", ""; +}; + +&gpio20 { + /* GPIO_160-GPIO_167 */ + gpio-line-names = + "[SD_CLK]", + "[SD_CMD]", + "[SD_DATA0]", + "[SD_DATA1]", + "[SD_DATA2]", + "[SD_DATA3]", + "", ""; +}; + +&gpio21 { + /* GPIO_168-GPIO_175 */ + gpio-line-names = + "[WL_SDIO_CLK]", + "[WL_SDIO_CMD]", + "[WL_SDIO_DATA0]", + "[WL_SDIO_DATA1]", + "[WL_SDIO_DATA2]", + "[WL_SDIO_DATA3]", + "", ""; +}; + +&gpio22 { + /* GPIO_176-GPIO_183 */ + gpio-line-names = + "[GPIO_176_PMU_PWR_HOLD]", + "NA", + "[SYSCLK_EN]", + "GPIO_179_WL_WAKEUP_AP", + "GPIO_180_HDMI_INT", + "NA", + "GPIO-F", /* LSEC pin 28: LCD_BL_PWM */ + "[I2C0_SCL]"; /* LSEC pin 15 */ +}; + +&gpio23 { + /* GPIO_184-GPIO_191 */ + gpio-line-names = + "[I2C0_SDA]", /* LSEC pin 17 */ + "[I2C1_SCL]", /* Actual SoC I2C1 */ + "[I2C1_SDA]", /* Actual SoC I2C1 */ + "[I2C1_SCL]", /* LSEC pin 19: I2C7_SCL */ + "[I2C1_SDA]", /* LSEC pin 21: I2C7_SDA */ + "GPIO_189_USER_LED3", + "GPIO_190_USER_LED4", + ""; +}; + +&gpio24 { + /* GPIO_192-GPIO_199 */ + gpio-line-names = + "[PCM_DI]", /* LSEC pin 22: GPIO_192_I2S0_DI */ + "[PCM_DO]", /* LSEC pin 20: GPIO_193_I2S0_DO */ + "[PCM_CLK]", /* LSEC pin 18: GPIO_194_I2S0_XCLK */ + "[PCM_FS]", /* LSEC pin 16: GPIO_195_I2S0_XFS */ + "[GPIO_196_I2S2_DI]", + "[GPIO_197_I2S2_DO]", + "[GPIO_198_I2S2_XCLK]", + "[GPIO_199_I2S2_XFS]"; +}; + +&gpio25 { + /* GPIO_200-GPIO_207 */ + gpio-line-names = + "NC", + "NC", + "GPIO_202_VBUS_TYPEC", + "GPIO_203_SD_DET", + "GPIO_204_PMU12_IRQ_N", + "GPIO_205_WIFI_ACTIVE", + "GPIO_206_USBSW_SEL", + "GPIO_207_BT_ACTIVE"; +}; + +&gpio26 { + /* GPIO_208-GPIO_215 */ + gpio-line-names = + "GPIO-A", /* LSEC pin 23: GPIO_208 */ + "GPIO-B", /* LSEC pin 24: GPIO_209 */ + "GPIO-C", /* LSEC pin 25: GPIO_210 */ + "GPIO-D", /* LSEC pin 26: GPIO_211 */ + "GPIO-E", /* LSEC pin 27: GPIO_212 */ + "[PCIE_CLKREQ_N]", + "[PCIE_WAKE_N]", + "[SPI0_CLK]"; /* LSEC pin 8: SPI2_CLK */ +}; + +&gpio27 { + /* GPIO_216-GPIO_223 */ + gpio-line-names = + "[SPI0_DIN]", /* LSEC pin 10: SPI2_DI */ + "[SPI0_DOUT]", /* LSEC pin 14: SPI2_DO */ + "[SPI0_CS]", /* LSEC pin 12: SPI2_CS0_N */ + "GPIO_219_CC_INT", + "NC", + "NC", + "[PMU_INT]", + ""; +}; + +&gpio28 { + /* GPIO_224-GPIO_231 */ + gpio-line-names = + "", "", "", "", "", "", "", ""; +}; + +&i2c0 { + /* On Low speed expansion */ + label = "LS-I2C0"; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + adv7533: adv7533@39 { + status = "ok"; + compatible = "adi,adv7533"; + reg = <0x39>; + }; +}; + +&i2c7 { + /* On Low speed expansion */ + label = "LS-I2C1"; + status = "okay"; +}; + +&uart3 { + /* On Low speed expansion */ + label = "LS-UART0"; + status = "okay"; +}; + +&uart4 { + status = "okay"; + + bluetooth { + compatible = "ti,wl1837-st"; + enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + }; +}; + +&uart6 { + /* On Low speed expansion */ + label = "LS-UART1"; + status = "okay"; +}; + +&spi2 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; +}; + +&spi3 { + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; +}; + +&dwmmc1 { + vmmc-supply = <&ldo16>; + vqmmc-supply = <&ldo9>; + status = "okay"; +}; + +&dwmmc2 { /* WIFI */ + broken-cd; + /* WL_EN */ + vmmc-supply = <&wlan_en>; + ti,non-removable; + non-removable; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "ok"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; /* sdio func num */ + /* WL_IRQ, GPIO_179_WL_WAKEUP_AP */ + interrupt-parent = <&gpio22>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + }; +}; diff --git a/Platforms/Hisilicon/DeviceTree/hi3660.dtsi b/Platforms/Hisilicon/DeviceTree/hi3660.dtsi new file mode 100644 index 0000000..63d4f9d --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hi3660.dtsi @@ -0,0 +1,1002 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Hisilicon Hi3660 SoC + * + * Copyright (C) 2016, Hisilicon Ltd. + */ + +#include +#include + +/ { + compatible = "hisilicon,hi3660"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <592>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <592>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <592>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <592>; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a73", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&A73_L2>; + cpu-idle-states = < + &CPU_NAP + &CPU_SLEEP + &CLUSTER_SLEEP_1 + >; + capacity-dmips-mhz = <1024>; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a73", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&A73_L2>; + cpu-idle-states = < + &CPU_NAP + &CPU_SLEEP + &CLUSTER_SLEEP_1 + >; + capacity-dmips-mhz = <1024>; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a73", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x102>; + enable-method = "psci"; + next-level-cache = <&A73_L2>; + cpu-idle-states = < + &CPU_NAP + &CPU_SLEEP + &CLUSTER_SLEEP_1 + >; + capacity-dmips-mhz = <1024>; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a73", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x103>; + enable-method = "psci"; + next-level-cache = <&A73_L2>; + cpu-idle-states = < + &CPU_NAP + &CPU_SLEEP + &CLUSTER_SLEEP_1 + >; + capacity-dmips-mhz = <1024>; + }; + + idle-states { + entry-method = "psci"; + + CPU_NAP: cpu-nap { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000001>; + entry-latency-us = <7>; + exit-latency-us = <2>; + min-residency-us = <15>; + }; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <70>; + min-residency-us = <3000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <5000>; + min-residency-us = <20000>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <1000>; + exit-latency-us = <5000>; + min-residency-us = <20000>; + }; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + + A73_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@e82b0000 { + compatible = "arm,gic-400"; + reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ + <0x0 0xe82b2000 0 0x2000>, /* GICC */ + <0x0 0xe82b4000 0 0x2000>, /* GICH */ + <0x0 0xe82b6000 0 0x2000>; /* GICV */ + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + a53-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + a73-pmu { + compatible = "arm,cortex-a73-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu4>, + <&cpu5>, + <&cpu6>, + <&cpu7>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + crg_ctrl: crg_ctrl@fff35000 { + compatible = "hisilicon,hi3660-crgctrl", "syscon"; + reg = <0x0 0xfff35000 0x0 0x1000>; + #clock-cells = <1>; + }; + + crg_rst: crg_rst_controller { + compatible = "hisilicon,hi3660-reset"; + #reset-cells = <2>; + hisi,rst-syscon = <&crg_ctrl>; + }; + + + pctrl: pctrl@e8a09000 { + compatible = "hisilicon,hi3660-pctrl", "syscon"; + reg = <0x0 0xe8a09000 0x0 0x2000>; + #clock-cells = <1>; + }; + + pmuctrl: crg_ctrl@fff34000 { + compatible = "hisilicon,hi3660-pmuctrl", "syscon"; + reg = <0x0 0xfff34000 0x0 0x1000>; + #clock-cells = <1>; + }; + + sctrl: sctrl@fff0a000 { + compatible = "hisilicon,hi3660-sctrl", "syscon"; + reg = <0x0 0xfff0a000 0x0 0x1000>; + #clock-cells = <1>; + }; + + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3660-iomcu", "syscon"; + reg = <0x0 0xffd7e000 0x0 0x1000>; + #clock-cells = <1>; + + }; + + iomcu_rst: reset { + compatible = "hisilicon,hi3660-reset"; + hisi,rst-syscon = <&iomcu>; + #reset-cells = <2>; + }; + + dual_timer0: timer@fff14000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfff14000 0x0 0x1000>; + interrupts = , + ; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + i2c0: i2c@ffd71000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd71000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; + resets = <&iomcu_rst 0x20 3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; + + i2c1: i2c@ffd72000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd72000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; + resets = <&iomcu_rst 0x20 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; + status = "disabled"; + }; + + i2c3: i2c@fdf0c000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0c000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; + resets = <&crg_rst 0x78 7>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; + status = "disabled"; + }; + + i2c7: i2c@fdf0b000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0b000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; + resets = <&crg_rst 0x60 14>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; + status = "disabled"; + }; + + uart0: serial@fdf02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf02000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; + status = "disabled"; + }; + + uart1: serial@fdf00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf00000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, + <&crg_ctrl HI3660_CLK_GATE_UART1>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; + status = "disabled"; + }; + + uart2: serial@fdf03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf03000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; + status = "disabled"; + }; + + uart3: serial@ffd74000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xffd74000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_FACTOR_UART3>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + status = "disabled"; + }; + + uart4: serial@fdf01000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf01000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, + <&crg_ctrl HI3660_CLK_GATE_UART4>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; + status = "disabled"; + }; + + uart5: serial@fdf05000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf05000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, + <&crg_ctrl HI3660_CLK_GATE_UART5>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; + status = "disabled"; + }; + + uart6: serial@fff32000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfff32000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_UART6>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; + status = "disabled"; + }; + + dma0: dma@fdf30000 { + compatible = "hisilicon,k3-dma-1.0"; + reg = <0x0 0xfdf30000 0x0 0x1000>; + #dma-cells = <1>; + dma-channels = <16>; + dma-requests = <32>; + dma-min-chan = <1>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; + dma-no-cci; + dma-type = "hi3660_dma"; + }; + + rtc0: rtc@fff04000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0Xfff04000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + }; + + gpio0: gpio@e8a0b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0b000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 1 0 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@e8a0c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0c000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 1 7 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@e8a0d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0d000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 14 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; + clock-names = "apb_pclk"; + }; + + gpio3: gpio@e8a0e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0e000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 22 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; + clock-names = "apb_pclk"; + }; + + gpio4: gpio@e8a0f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a0f000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 30 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; + clock-names = "apb_pclk"; + }; + + gpio5: gpio@e8a10000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a10000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 38 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; + clock-names = "apb_pclk"; + }; + + gpio6: gpio@e8a11000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a11000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 46 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; + clock-names = "apb_pclk"; + }; + + gpio7: gpio@e8a12000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a12000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 54 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; + clock-names = "apb_pclk"; + }; + + gpio8: gpio@e8a13000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a13000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 62 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; + clock-names = "apb_pclk"; + }; + + gpio9: gpio@e8a14000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a14000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 70 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; + clock-names = "apb_pclk"; + }; + + gpio10: gpio@e8a15000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a15000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 78 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; + clock-names = "apb_pclk"; + }; + + gpio11: gpio@e8a16000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a16000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 86 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; + clock-names = "apb_pclk"; + }; + + gpio12: gpio@e8a17000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a17000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; + clock-names = "apb_pclk"; + }; + + gpio13: gpio@e8a18000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a18000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 102 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; + clock-names = "apb_pclk"; + }; + + gpio14: gpio@e8a19000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a19000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 110 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; + clock-names = "apb_pclk"; + }; + + gpio15: gpio@e8a1a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1a000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 118 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; + clock-names = "apb_pclk"; + }; + + gpio16: gpio@e8a1b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1b000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; + clock-names = "apb_pclk"; + }; + + gpio17: gpio@e8a1c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1c000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; + clock-names = "apb_pclk"; + }; + + gpio18: gpio@ff3b4000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xff3b4000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx2 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; + clock-names = "apb_pclk"; + }; + + gpio19: gpio@ff3b5000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xff3b5000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx2 0 8 4>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; + clock-names = "apb_pclk"; + }; + + gpio20: gpio@e8a1f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a1f000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx1 0 0 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; + clock-names = "apb_pclk"; + }; + + gpio21: gpio@e8a20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xe8a20000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&pmx3 0 0 6>; + clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; + clock-names = "apb_pclk"; + }; + + gpio22: gpio@fff0b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0b000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO176 */ + gpio-ranges = <&pmx4 2 0 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; + clock-names = "apb_pclk"; + }; + + gpio23: gpio@fff0c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0c000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO184 */ + gpio-ranges = <&pmx4 0 6 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; + clock-names = "apb_pclk"; + }; + + gpio24: gpio@fff0d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0d000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO192 */ + gpio-ranges = <&pmx4 0 13 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; + clock-names = "apb_pclk"; + }; + + gpio25: gpio@fff0e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0e000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO200 */ + gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; + clock-names = "apb_pclk"; + }; + + gpio26: gpio@fff0f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff0f000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO208 */ + gpio-ranges = <&pmx4 0 28 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; + clock-names = "apb_pclk"; + }; + + gpio27: gpio@fff10000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff10000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + /* GPIO216 */ + gpio-ranges = <&pmx4 0 36 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; + clock-names = "apb_pclk"; + }; + + gpio28: gpio@fff1d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0 0xfff1d000 0 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; + clock-names = "apb_pclk"; + }; + + spi2: spi@ffd68000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xffd68000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio27 2 0>; + status = "disabled"; + }; + + spi3: spi@ff3b3000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xff3b3000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio18 5 0>; + status = "disabled"; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + }; + + /* SD */ + dwmmc1: dwmmc1@ff37f000 { + #address-cells = <1>; + #size-cells = <0>; + cd-inverted; + compatible = "hisilicon,hi3660-dw-mshc"; + num-slots = <1>; + bus-width = <0x4>; + disable-wp; + cap-sd-highspeed; + supports-highspeed; + card-detect-delay = <200>; + reg = <0x0 0xff37f000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, + <&crg_ctrl HI3660_HCLK_GATE_SD>; + clock-names = "ciu", "biu"; + clock-frequency = <3200000>; + resets = <&crg_rst 0x94 18>; + reset-names = "reset"; + cd-gpios = <&gpio25 3 0>; + hisilicon,peripheral-syscon = <&sctrl>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pmx_func + &sd_clk_cfg_func + &sd_cfg_func>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "disabled"; + + slot@0 { + reg = <0x0>; + bus-width = <4>; + disable-wp; + }; + }; + + /* SDIO */ + dwmmc2: dwmmc2@ff3ff000 { + compatible = "hisilicon,hi3660-dw-mshc"; + reg = <0x0 0xff3ff000 0x0 0x1000>; + interrupts = ; + num-slots = <1>; + clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, + <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; + clock-names = "ciu", "biu"; + resets = <&crg_rst 0x94 20>; + reset-names = "reset"; + card-detect-delay = <200>; + supports-highspeed; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_pmx_func + &sdio_clk_cfg_func + &sdio_cfg_func>; + status = "disabled"; + }; + + watchdog0: watchdog@e8a06000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xe8a06000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_OSC32K>; + clock-names = "apb_pclk"; + }; + + watchdog1: watchdog@e8a07000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xe8a07000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_OSC32K>; + clock-names = "apb_pclk"; + }; + + tsensor: tsensor@fff30000 { + compatible = "hisilicon,hi3660-tsensor"; + reg = <0x0 0xfff30000 0x0 0x1000>; + interrupts = ; + #thermal-sensor-cells = <1>; + }; + }; +}; diff --git a/Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dtb b/Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dtb new file mode 100644 index 0000000..50a07b6 Binary files /dev/null and b/Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dtb differ diff --git a/Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dts b/Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dts new file mode 100644 index 0000000..4d5d644 --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dts @@ -0,0 +1,168 @@ +/* + * DTS File for HiSilicon Poplar Development Board + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * Released under the GPLv2 only. + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; + +#include +#include "hi3798cv200.dtsi" + +/ { + model = "HiSilicon Poplar Development Board"; + compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; + + aliases { + serial0 = &uart0; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + + user-led0 { + label = "USER-LED0"; + gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + user-led1 { + label = "USER-LED1"; + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + user-led2 { + label = "USER-LED2"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + user-led3 { + label = "USER-LED3"; + gpios = <&gpio10 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + }; +}; + +&gmac1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <ð_phy1>; + phy-mode = "rgmii"; + hisilicon,phy-reset-delays-us = <10000 10000 30000>; + + eth_phy1: phy@3 { + reg = <3>; + }; +}; + +&gpio1 { + status = "okay"; + gpio-line-names = "GPIO-E", "", + "", "", + "", "GPIO-F", + "", "GPIO-J"; +}; + +&gpio2 { + status = "okay"; + gpio-line-names = "GPIO-H", "GPIO-I", + "GPIO-L", "GPIO-G", + "GPIO-K", "", + "", ""; +}; + +&gpio3 { + status = "okay"; + gpio-line-names = "", "", + "", "", + "GPIO-C", "", + "", "GPIO-B"; +}; + +&gpio4 { + status = "okay"; + gpio-line-names = "", "", + "", "", + "", "GPIO-D", + "", ""; +}; + +&gpio5 { + status = "okay"; + gpio-line-names = "", "USER-LED-1", + "USER-LED-2", "", + "", "GPIO-A", + "", ""; +}; + +&gpio6 { + status = "okay"; + gpio-line-names = "", "", + "", "USER-LED-0", + "", "", + "", ""; +}; + +&gpio10 { + status = "okay"; + gpio-line-names = "", "", + "", "", + "", "", + "USER-LED-3", ""; +}; + +&i2c0 { + status = "okay"; + label = "LS-I2C0"; +}; + +&i2c2 { + status = "okay"; + label = "LS-I2C1"; +}; + +&ir { + status = "okay"; +}; + +&sd0 { + bus-width = <4>; + cap-sd-highspeed; + status = "okay"; +}; + +&spi0 { + status = "okay"; + label = "LS-SPI0"; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + label = "LS-UART0"; +}; +/* No optional LS-UART1 on Low Speed Expansion Connector. */ diff --git a/Platforms/Hisilicon/DeviceTree/hi3798cv200.dtsi b/Platforms/Hisilicon/DeviceTree/hi3798cv200.dtsi new file mode 100644 index 0000000..962bd79 --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hi3798cv200.dtsi @@ -0,0 +1,423 @@ +/* + * DTS File for HiSilicon Hi3798cv200 SoC. + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * Released under the GPLv2 only. + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include + +/ { + compatible = "hisilicon,hi3798cv200"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ + <0x0 0xf1002000 0x0 0x100>; /* GICC */ + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc: soc@f0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xf0000000 0x10000000>; + + crg: clock-reset-controller@8a22000 { + compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; + reg = <0x8a22000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + + gmacphyrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = + <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | + DEASSERT_SET|STATUS_NONE)>, + <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | + DEASSERT_SET|STATUS_NONE)>; + }; + }; + + sysctrl: system-controller@8000000 { + compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; + reg = <0x8000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + }; + + uart0: serial@8b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x8b00000 0x1000>; + interrupts = ; + clocks = <&sysctrl HISTB_UART0_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@8b02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x8b02000 0x1000>; + interrupts = ; + clocks = <&crg HISTB_UART2_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@8b10000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b10000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C0_CLK>; + status = "disabled"; + }; + + i2c1: i2c@8b11000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b11000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C1_CLK>; + status = "disabled"; + }; + + i2c2: i2c@8b12000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b12000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C2_CLK>; + status = "disabled"; + }; + + i2c3: i2c@8b13000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b13000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C3_CLK>; + status = "disabled"; + }; + + i2c4: i2c@8b14000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b14000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C4_CLK>; + status = "disabled"; + }; + + spi0: spi@8b1a000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x8b1a000 0x1000>; + interrupts = ; + num-cs = <1>; + cs-gpios = <&gpio7 1 0>; + clocks = <&crg HISTB_SPI0_CLK>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sd0: mmc@9820000 { + compatible = "snps,dw-mshc"; + reg = <0x9820000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_SDIO0_CIU_CLK>, + <&crg HISTB_SDIO0_BIU_CLK>; + clock-names = "ciu", "biu"; + resets = <&crg 0x9c 4>; + reset-names = "reset"; + status = "disabled"; + }; + + emmc: mmc@9830000 { + compatible = "snps,dw-mshc"; + reg = <0x9830000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>; + clock-names = "ciu", "biu"; + }; + + gpio0: gpio@8b20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b20000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio1: gpio@8b21000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b21000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio2: gpio@8b22000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b22000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio3: gpio@8b23000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b23000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio4: gpio@8b24000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b24000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio5: gpio@8004000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8004000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio6: gpio@8b26000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b26000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio7: gpio@8b27000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b27000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio8: gpio@8b28000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b28000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio9: gpio@8b29000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b29000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio10: gpio@8b2a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b2a000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio11: gpio@8b2b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b2b000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio12: gpio@8b2c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b2c000 0x1000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gmac0: ethernet@9840000 { + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0x9840000 0x1000>, + <0x984300c 0x4>; + interrupts = ; + clocks = <&crg HISTB_ETH0_MAC_CLK>, + <&crg HISTB_ETH0_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 8>, + <&crg 0xcc 10>, + <&gmacphyrst 0>; + reset-names = "mac_core", "mac_ifc", "phy"; + status = "disabled"; + }; + + gmac1: ethernet@9841000 { + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0x9841000 0x1000>, + <0x9843010 0x4>; + interrupts = ; + clocks = <&crg HISTB_ETH1_MAC_CLK>, + <&crg HISTB_ETH1_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 9>, + <&crg 0xcc 11>, + <&gmacphyrst 1>; + reset-names = "mac_core", "mac_ifc", "phy"; + status = "disabled"; + }; + + ir: ir@8001000 { + compatible = "hisilicon,hix5hd2-ir"; + reg = <0x8001000 0x1000>; + interrupts = ; + clocks = <&sysctrl HISTB_IR_CLK>; + status = "disabled"; + }; + }; +}; diff --git a/Platforms/Hisilicon/DeviceTree/hi6220-coresight.dtsi b/Platforms/Hisilicon/DeviceTree/hi6220-coresight.dtsi new file mode 100644 index 0000000..7afee5d --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hi6220-coresight.dtsi @@ -0,0 +1,381 @@ +/* + * dtsi file for Hisilicon Hi6220 coresight + * + * Copyright (C) 2017 Hisilicon Ltd. + * + * Author: Pengcheng Li + * Leo Yan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +/ { + soc { + funnel@f6401000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xf6401000 0 0x1000>; + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + soc_funnel_out: endpoint { + remote-endpoint = + <&etf_in>; + }; + }; + + port@1 { + reg = <0>; + soc_funnel_in: endpoint { + slave-mode; + remote-endpoint = + <&acpu_funnel_out>; + }; + }; + }; + }; + + etf@f6402000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xf6402000 0 0x1000>; + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etf_in: endpoint { + slave-mode; + remote-endpoint = + <&soc_funnel_out>; + }; + }; + + port@1 { + reg = <0>; + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + }; + + replicator { + compatible = "arm,coresight-replicator"; + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_in: endpoint { + slave-mode; + remote-endpoint = + <&etf_out>; + }; + }; + + port@1 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = + <&etr_in>; + }; + }; + + port@2 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = + <&tpiu_in>; + }; + }; + }; + }; + + etr@f6404000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xf6404000 0 0x1000>; + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etr_in: endpoint { + slave-mode; + remote-endpoint = + <&replicator_out0>; + }; + }; + }; + }; + + tpiu@f6405000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0xf6405000 0 0x1000>; + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpiu_in: endpoint { + slave-mode; + remote-endpoint = + <&replicator_out1>; + }; + }; + }; + }; + + funnel@f6501000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xf6501000 0 0x1000>; + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + acpu_funnel_out: endpoint { + remote-endpoint = + <&soc_funnel_in>; + }; + }; + + port@1 { + reg = <0>; + acpu_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out>; + }; + }; + + port@2 { + reg = <1>; + acpu_funnel_in1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out>; + }; + }; + + port@3 { + reg = <2>; + acpu_funnel_in2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out>; + }; + }; + + port@4 { + reg = <3>; + acpu_funnel_in3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out>; + }; + }; + + port@5 { + reg = <4>; + acpu_funnel_in4: endpoint { + slave-mode; + remote-endpoint = + <&etm4_out>; + }; + }; + + port@6 { + reg = <5>; + acpu_funnel_in5: endpoint { + slave-mode; + remote-endpoint = + <&etm5_out>; + }; + }; + + port@7 { + reg = <6>; + acpu_funnel_in6: endpoint { + slave-mode; + remote-endpoint = + <&etm6_out>; + }; + }; + + port@8 { + reg = <7>; + acpu_funnel_in7: endpoint { + slave-mode; + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + etm@f659c000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf659c000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu0>; + + port { + etm0_out: endpoint { + remote-endpoint = + <&acpu_funnel_in0>; + }; + }; + }; + + etm@f659d000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf659d000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu1>; + + port { + etm1_out: endpoint { + remote-endpoint = + <&acpu_funnel_in1>; + }; + }; + }; + + etm@f659e000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf659e000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu2>; + + port { + etm2_out: endpoint { + remote-endpoint = + <&acpu_funnel_in2>; + }; + }; + }; + + etm@f659f000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf659f000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu3>; + + port { + etm3_out: endpoint { + remote-endpoint = + <&acpu_funnel_in3>; + }; + }; + }; + + etm@f65dc000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf65dc000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu4>; + + port { + etm4_out: endpoint { + remote-endpoint = + <&acpu_funnel_in4>; + }; + }; + }; + + etm@f65dd000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf65dd000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu5>; + + port { + etm5_out: endpoint { + remote-endpoint = + <&acpu_funnel_in5>; + }; + }; + }; + + etm@f65de000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf65de000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu6>; + + port { + etm6_out: endpoint { + remote-endpoint = + <&acpu_funnel_in6>; + }; + }; + }; + + etm@f65df000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xf65df000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu7>; + + port { + etm7_out: endpoint { + remote-endpoint = + <&acpu_funnel_in7>; + }; + }; + }; + }; +}; diff --git a/Platforms/Hisilicon/DeviceTree/hi6220-hikey.dtb b/Platforms/Hisilicon/DeviceTree/hi6220-hikey.dtb new file mode 100644 index 0000000..8e0872f Binary files /dev/null and b/Platforms/Hisilicon/DeviceTree/hi6220-hikey.dtb differ diff --git a/Platforms/Hisilicon/DeviceTree/hi6220-hikey.dts b/Platforms/Hisilicon/DeviceTree/hi6220-hikey.dts new file mode 100644 index 0000000..e94fa1a --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hi6220-hikey.dts @@ -0,0 +1,548 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Hisilicon HiKey Development Board + * + * Copyright (C) 2015, Hisilicon Ltd. + * + */ + +/dts-v1/; +#include "hi6220.dtsi" +#include "hikey-pinctrl.dtsi" +#include + +/ { + model = "HiKey Development Board"; + compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; + + aliases { + serial0 = &uart0; /* On board UART0 */ + serial1 = &uart1; /* BT UART */ + serial2 = &uart2; /* LS Expansion UART0 */ + serial3 = &uart3; /* LS Expansion UART1 */ + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + /* + * Reserve below regions from memory node: + * + * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using + * 0x05f0,1000 - 0x05f0,1fff: Reboot reason + * 0x06df,f000 - 0x06df,ffff: Mailbox message data + * 0x0740,f000 - 0x0740,ffff: MCU firmware section + * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer + * 0x3e00,0000 - 0x3fff,ffff: OP-TEE + */ + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x05e00000>, + <0x00000000 0x05f00000 0x00000000 0x00001000>, + <0x00000000 0x05f02000 0x00000000 0x00efd000>, + <0x00000000 0x06e00000 0x00000000 0x0060f000>, + <0x00000000 0x07410000 0x00000000 0x1aaf0000>, + <0x00000000 0x22000000 0x00000000 0x1c000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@0x21f00000 { + compatible = "ramoops"; + reg = <0x0 0x21f00000 0x0 0x00100000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00000000 0x08000000>; + linux,cma-default; + }; + }; + + reboot-mode-syscon@5f01000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x05f01000 0x0 0x00001000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x0>; + + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; + }; + }; + + reg_sys_5v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "SYS_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <®_sys_5v>; + }; + + reg_5v_hub: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "5V_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio0 7 0>; + regulator-always-on; + vin-supply = <®_sys_5v>; + }; + + wl1835_pwrseq: wl1835-pwrseq { + compatible = "mmc-pwrseq-simple"; + /* WLAN_EN GPIO */ + reset-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + clocks = <&pmic>; + clock-names = "ext_clock"; + power-off-delay-us = <10>; + }; + + soc { + spi0: spi@f7106000 { + status = "ok"; + }; + + i2c0: i2c@f7100000 { + status = "ok"; + }; + + i2c1: i2c@f7101000 { + status = "ok"; + }; + + uart1: uart@f7111000 { + assigned-clocks = <&sys_ctrl HI6220_UART1_SRC>; + assigned-clock-rates = <150000000>; + status = "ok"; + + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + clocks = <&pmic>; + clock-names = "ext_clock"; + }; + }; + + uart2: uart@f7112000 { + status = "ok"; + }; + + uart3: uart@f7113000 { + status = "ok"; + }; + + /* + * Legend: proper name = the GPIO line is used as GPIO + * NC = not connected (not routed from the SoC) + * "[PER]" = pin is muxed for peripheral (not GPIO) + * "" = no idea, schematic doesn't say, could be + * unrouted (not connected to any external pin) + * LSEC = Low Speed External Connector + * HSEC = High Speed External Connector + * + * Pin assignments taken from LeMaker and CircuitCo Schematics + * Rev A1. + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART2. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ + gpio0: gpio@f8011000 { + gpio-line-names = "PWR_HOLD", "DSI_SEL", + "USB_HUB_RESET_N", "USB_SEL", "HDMI_PD", "WL_REG_ON", + "PWRON_DET", "5V_HUB_EN"; + }; + + gpio1: gpio@f8012000 { + gpio-line-names = "SD_DET", "HDMI_INT", "PMU_IRQ_N", + "WL_HOST_WAKE", "NC", "NC", "NC", "BT_REG_ON"; + }; + + gpio2: gpio@f8013000 { + gpio-line-names = + "GPIO-A", /* LSEC Pin 23: GPIO2_0 */ + "GPIO-B", /* LSEC Pin 24: GPIO2_1 */ + "GPIO-C", /* LSEC Pin 25: GPIO2_2 */ + "GPIO-D", /* LSEC Pin 26: GPIO2_3 */ + "GPIO-E", /* LSEC Pin 27: GPIO2_4 */ + "USB_ID_DET", "USB_VBUS_DET", + "GPIO-H"; /* LSEC Pin 30: GPIO2_7 */ + }; + + gpio3: gpio@f8014000 { + gpio-line-names = "GPIO3_0", "NC", "NC", "", "NC", "", + "WLAN_ACTIVE", "NC", "NC"; + }; + + gpio4: gpio@f7020000 { + gpio-line-names = "USER_LED1", "USER_LED2", "USER_LED3", + "USER_LED4", "SD_SEL", "NC", "NC", "BT_ACTIVE"; + }; + + gpio5: gpio@f7021000 { + gpio-line-names = "NC", "NC", + "[UART1_RxD]", /* LSEC Pin 11: UART3_RX */ + "[UART1_TxD]", /* LSEC Pin 13: UART3_TX */ + "[AUX_SSI1]", "NC", + "[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */ + "[PCM_FS]"; /* LSEC Pin 16: MODEM_PCM_XFS */ + }; + + gpio6: gpio@f7022000 { + gpio-line-names = + "[SPI0_DIN]", /* Pin 10: SPI0_DI */ + "[SPI0_DOUT]", /* Pin 14: SPI0_DO */ + "[SPI0_CS]", /* Pin 12: SPI0_CS_N */ + "[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */ + "NC", "NC", "NC", + "GPIO-G"; /* Pin 29: GPIO6_7_DSI_TE0 */ + }; + + gpio7: gpio@f7023000 { + gpio-line-names = "NC", "NC", "NC", "NC", + "[PCM_DI]", /* Pin 22: MODEM_PCM_DI */ + "[PCM_DO]", /* Pin 20: MODEM_PCM_DO */ + "NC", "NC"; + }; + + gpio8: gpio@f7024000 { + gpio-line-names = "NC", "[CEC_CLK_19_2MHZ]", "NC", + "", "", "", "", "", ""; + }; + + gpio9: gpio@f7025000 { + gpio-line-names = "", + "GPIO-J", /* LSEC Pin 32: ISP_PWDN0_GPIO9_1 */ + "GPIO-L", /* LSEC Pin 34: ISP_PWDN1_GPIO9_2 */ + "NC", "NC", "NC", "NC", "[ISP_CCLK0]"; + }; + + gpio10: gpio@f7026000 { + gpio-line-names = "BOOT_SEL", + "[ISP_CCLK1]", + "GPIO-I", /* LSEC Pin 31: ISP_RSTB0_GPIO10_2 */ + "GPIO-K", /* LSEC Pin 33: ISP_RSTB1_GPIO10_3 */ + "NC", "NC", + "[I2C2_SDA]", /* HSEC Pin 34: ISP0_SDA */ + "[I2C2_SCL]"; /* HSEC Pin 32: ISP0_SCL */ + }; + + gpio11: gpio@f7027000 { + gpio-line-names = + "[I2C3_SDA]", /* HSEC Pin 38: ISP1_SDA */ + "[I2C3_SCL]", /* HSEC Pin 36: ISP1_SCL */ + "", "NC", "NC", "NC", "", ""; + }; + + gpio12: gpio@f7028000 { + gpio-line-names = "[BT_PCM_XFS]", "[BT_PCM_DI]", + "[BT_PCM_DO]", + "NC", "NC", "NC", "NC", + "GPIO-F"; /* LSEC Pin 28: BL_PWM_GPIO12_7 */ + }; + + gpio13: gpio@f7029000 { + gpio-line-names = "[UART0_RX]", "[UART0_TX]", + "[BT_UART1_CTS]", "[BT_UART1_RTS]", + "[BT_UART1_RX]", "[BT_UART1_TX]", + "[UART0_CTS]", /* LSEC Pin 3: UART2_CTS_N */ + "[UART0_RTS]"; /* LSEC Pin 9: UART2_RTS_N */ + }; + + gpio14: gpio@f702a000 { + gpio-line-names = + "[UART0_RxD]", /* LSEC Pin 7: UART2_RX */ + "[UART0_TxD]", /* LSEC Pin 5: UART2_TX */ + "[I2C0_SCL]", /* LSEC Pin 15: I2C0_SCL */ + "[I2C0_SDA]", /* LSEC Pin 17: I2C0_SDA */ + "[I2C1_SCL]", /* LSEC Pin 19: I2C1_SCL */ + "[I2C1_SDA]", /* LSEC Pin 21: I2C1_SDA */ + "[I2C2_SCL]", "[I2C2_SDA]"; + }; + + gpio15: gpio@f702b000 { + gpio-line-names = "", "", "", "", "", "", "NC", ""; + }; + + /* GPIO blocks 16 thru 19 do not appear to be routed to pins */ + + dwmmc_0: dwmmc0@f723d000 { + cap-mmc-highspeed; + non-removable; + bus-width = <0x8>; + vmmc-supply = <&ldo19>; + }; + + dwmmc_1: dwmmc1@f723e000 { + card-detect-delay = <200>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + vqmmc-supply = <&ldo7>; + vmmc-supply = <&ldo10>; + bus-width = <0x4>; + disable-wp; + cd-gpios = <&gpio1 0 1>; + }; + + dwmmc_2: dwmmc2@f723f000 { + bus-width = <0x4>; + non-removable; + vmmc-supply = <®_vdd_3v3>; + mmc-pwrseq = <&wl1835_pwrseq>; + + #address-cells = <0x1>; + #size-cells = <0x0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; /* sdio func num */ + /* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */ + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + user_led4 { + label = "user_led4"; + gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */ + linux,default-trigger = "heartbeat"; + }; + + user_led3 { + label = "user_led3"; + gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */ + linux,default-trigger = "mmc0"; + }; + + user_led2 { + label = "user_led2"; + gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */ + linux,default-trigger = "mmc1"; + }; + + user_led1 { + label = "user_led1"; + gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */ + panic-indicator; + linux,default-trigger = "cpu0"; + }; + + wlan_active_led { + label = "wifi_active"; + gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */ + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt_active_led { + label = "bt_active"; + gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */ + linux,default-trigger = "hci0rx"; + default-state = "off"; + }; + }; + + pmic: pmic@f8000000 { + compatible = "hisilicon,hi655x-pmic"; + reg = <0x0 0xf8000000 0x0 0x1000>; + #clock-cells = <0>; + interrupt-controller; + #interrupt-cells = <2>; + pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + + regulators { + ldo2: LDO2 { + regulator-name = "LDO2_2V8"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo7: LDO7 { + regulator-name = "LDO7_SDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo10: LDO10 { + regulator-name = "LDO10_2V85"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <360>; + }; + + ldo13: LDO13 { + regulator-name = "LDO13_1V8"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo14: LDO14 { + regulator-name = "LDO14_2V8"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo15: LDO15 { + regulator-name = "LDO15_1V8"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + regulator-enable-ramp-delay = <120>; + }; + + ldo17: LDO17 { + regulator-name = "LDO17_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo19: LDO19 { + regulator-name = "LDO19_3V0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <360>; + }; + + ldo21: LDO21 { + regulator-name = "LDO21_1V8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + regulator-enable-ramp-delay = <120>; + }; + + ldo22: LDO22 { + regulator-name = "LDO22_1V2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + regulator-enable-ramp-delay = <120>; + }; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + sound_card { + compatible = "audio-graph-card"; + dais = <&i2s0_port0>; + }; +}; + +&uart2 { + label = "LS-UART0"; +}; +&uart3 { + label = "LS-UART1"; +}; + +&ade { + status = "ok"; +}; + +&dsi { + status = "ok"; + + ports { + /* 1 for output port */ + port@1 { + reg = <1>; + + dsi_out0: endpoint@0 { + remote-endpoint = <&adv7533_in>; + }; + }; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + adv7533: adv7533@39 { + compatible = "adi,adv7533"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <1 2>; + pd-gpio = <&gpio0 4 0>; + adi,dsi-lanes = <4>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + adv7533_in: endpoint { + remote-endpoint = <&dsi_out0>; + }; + }; + port@2 { + reg = <2>; + codec_endpoint: endpoint { + remote-endpoint = <&i2s0_cpu_endpoint>; + }; + }; + }; + }; +}; + +&i2s0 { + + ports { + i2s0_port0: port@0 { + i2s0_cpu_endpoint: endpoint { + remote-endpoint = <&codec_endpoint>; + dai-format = "i2s"; + }; + }; + }; +}; diff --git a/Platforms/Hisilicon/DeviceTree/hi6220.dtsi b/Platforms/Hisilicon/DeviceTree/hi6220.dtsi new file mode 100644 index 0000000..6a180d1 --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hi6220.dtsi @@ -0,0 +1,991 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Hisilicon Hi6220 SoC + * + * Copyright (C) 2015, Hisilicon Ltd. + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "hisilicon,hi6220"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <700>; + exit-latency-us = <250>; + min-residency-us = <1000>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + clocks = <&stub_clock 0>; + operating-points-v2 = <&cpu_opp_table>; + cooling-min-level = <4>; + cooling-max-level = <0>; + #cooling-cells = <2>; /* min followed by max */ + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + dynamic-power-coefficient = <311>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x102>; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x103>; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + CLUSTER0_L2: l2-cache0 { + compatible = "cache"; + }; + + CLUSTER1_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <208000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <500000>; + }; + opp01 { + opp-hz = /bits/ 64 <432000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <500000>; + }; + opp02 { + opp-hz = /bits/ 64 <729000000>; + opp-microvolt = <1090000>; + clock-latency-ns = <500000>; + }; + opp03 { + opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <1180000>; + clock-latency-ns = <500000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1330000>; + clock-latency-ns = <500000>; + }; + }; + + gic: interrupt-controller@f6801000 { + compatible = "arm,gic-400"; + reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ + <0x0 0xf6802000 0 0x2000>, /* GICC */ + <0x0 0xf6804000 0 0x2000>, /* GICH */ + <0x0 0xf6806000 0 0x2000>; /* GICV */ + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sram: sram@fff80000 { + compatible = "hisilicon,hi6220-sramctrl", "syscon"; + reg = <0x0 0xfff80000 0x0 0x12000>; + }; + + ao_ctrl: ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0x0 0xf7800000 0x0 0x2000>; + #clock-cells = <1>; + }; + + sys_ctrl: sys_ctrl@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0x0 0xf7030000 0x0 0x2000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + media_ctrl: media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0x0 0xf4410000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pm_ctrl: pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0x0 0xf7032000 0x0 0x1000>; + #clock-cells = <1>; + }; + + acpu_sctrl: acpu_sctrl@f6504000 { + compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; + reg = <0x0 0xf6504000 0x0 0x1000>; + #clock-cells = <1>; + }; + + medianoc_ade: medianoc_ade@f4520000 { + compatible = "syscon"; + reg = <0x0 0xf4520000 0x0 0x4000>; + }; + + stub_clock: stub_clock { + compatible = "hisilicon,hi6220-stub-clk"; + hisilicon,hi6220-clk-sram = <&sram>; + #clock-cells = <1>; + mbox-names = "mbox-tx"; + mboxes = <&mailbox 1 0 11>; + }; + + uart0: uart@f8015000 { /* console */ + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf8015000 0x0 0x1000>; + interrupts = ; + clocks = <&ao_ctrl HI6220_UART0_PCLK>, + <&ao_ctrl HI6220_UART0_PCLK>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: uart@f7111000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7111000 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl HI6220_UART1_PCLK>, + <&sys_ctrl HI6220_UART1_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; + status = "disabled"; + }; + + uart2: uart@f7112000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7112000 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl HI6220_UART2_PCLK>, + <&sys_ctrl HI6220_UART2_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; + status = "disabled"; + }; + + uart3: uart@f7113000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7113000 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl HI6220_UART3_PCLK>, + <&sys_ctrl HI6220_UART3_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + status = "disabled"; + }; + + uart4: uart@f7114000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xf7114000 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl HI6220_UART4_PCLK>, + <&sys_ctrl HI6220_UART4_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; + status = "disabled"; + }; + + dma0: dma@f7370000 { + compatible = "hisilicon,k3-dma-1.0"; + reg = <0x0 0xf7370000 0x0 0x1000>; + #dma-cells = <1>; + dma-channels = <15>; + dma-requests = <32>; + interrupts = <0 84 4>; + clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; + dma-no-cci; + dma-type = "hi6220_dma"; + status = "ok"; + }; + + dual_timer0: timer@f8008000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xf8008000 0x0 0x1000>; + interrupts = , + ; + clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, + <&ao_ctrl HI6220_TIMER0_PCLK>, + <&ao_ctrl HI6220_TIMER0_PCLK>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + rtc0: rtc@f8003000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0xf8003000 0x0 0x1000>; + interrupts = <0 12 4>; + clocks = <&ao_ctrl HI6220_RTC0_PCLK>; + clock-names = "apb_pclk"; + }; + + rtc1: rtc@f8004000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0xf8004000 0x0 0x1000>; + interrupts = <0 8 4>; + clocks = <&ao_ctrl HI6220_RTC1_PCLK>; + clock-names = "apb_pclk"; + }; + + pmx0: pinmux@f7010000 { + compatible = "pinctrl-single"; + reg = <0x0 0xf7010000 0x0 0x27c>; + #address-cells = <1>; + #size-cells = <1>; + #pinctrl-cells = <1>; + #gpio-range-cells = <3>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + pinctrl-single,gpio-range = < + &range 80 8 MUX_M0 /* gpio 3: [0..7] */ + &range 88 8 MUX_M0 /* gpio 4: [0..7] */ + &range 96 8 MUX_M0 /* gpio 5: [0..7] */ + &range 104 8 MUX_M0 /* gpio 6: [0..7] */ + &range 112 8 MUX_M0 /* gpio 7: [0..7] */ + &range 120 2 MUX_M0 /* gpio 8: [0..1] */ + &range 2 6 MUX_M1 /* gpio 8: [2..7] */ + &range 8 8 MUX_M1 /* gpio 9: [0..7] */ + &range 0 1 MUX_M1 /* gpio 10: [0] */ + &range 16 7 MUX_M1 /* gpio 10: [1..7] */ + &range 23 3 MUX_M1 /* gpio 11: [0..2] */ + &range 28 5 MUX_M1 /* gpio 11: [3..7] */ + &range 33 3 MUX_M1 /* gpio 12: [0..2] */ + &range 43 5 MUX_M1 /* gpio 12: [3..7] */ + &range 48 8 MUX_M1 /* gpio 13: [0..7] */ + &range 56 8 MUX_M1 /* gpio 14: [0..7] */ + &range 74 6 MUX_M1 /* gpio 15: [0..5] */ + &range 122 1 MUX_M1 /* gpio 15: [6] */ + &range 126 1 MUX_M1 /* gpio 15: [7] */ + &range 127 8 MUX_M1 /* gpio 16: [0..7] */ + &range 135 8 MUX_M1 /* gpio 17: [0..7] */ + &range 143 8 MUX_M1 /* gpio 18: [0..7] */ + &range 151 8 MUX_M1 /* gpio 19: [0..7] */ + >; + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + }; + + pmx1: pinmux@f7010800 { + compatible = "pinconf-single"; + reg = <0x0 0xf7010800 0x0 0x28c>; + #address-cells = <1>; + #size-cells = <1>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + }; + + pmx2: pinmux@f8001800 { + compatible = "pinconf-single"; + reg = <0x0 0xf8001800 0x0 0x78>; + #address-cells = <1>; + #size-cells = <1>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + }; + + gpio0: gpio@f8011000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf8011000 0x0 0x1000>; + interrupts = <0 52 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@f8012000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf8012000 0x0 0x1000>; + interrupts = <0 53 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@f8013000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf8013000 0x0 0x1000>; + interrupts = <0 54 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio3: gpio@f8014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf8014000 0x0 0x1000>; + interrupts = <0 55 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 80 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio4: gpio@f7020000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7020000 0x0 0x1000>; + interrupts = <0 56 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 88 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio5: gpio@f7021000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7021000 0x0 0x1000>; + interrupts = <0 57 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 96 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio6: gpio@f7022000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7022000 0x0 0x1000>; + interrupts = <0 58 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 104 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio7: gpio@f7023000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7023000 0x0 0x1000>; + interrupts = <0 59 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 112 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio8: gpio@f7024000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7024000 0x0 0x1000>; + interrupts = <0 60 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio9: gpio@f7025000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7025000 0x0 0x1000>; + interrupts = <0 61 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 8 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio10: gpio@f7026000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7026000 0x0 0x1000>; + interrupts = <0 62 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio11: gpio@f7027000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7027000 0x0 0x1000>; + interrupts = <0 63 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio12: gpio@f7028000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7028000 0x0 0x1000>; + interrupts = <0 64 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio13: gpio@f7029000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf7029000 0x0 0x1000>; + interrupts = <0 65 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 48 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio14: gpio@f702a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702a000 0x0 0x1000>; + interrupts = <0 66 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 56 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio15: gpio@f702b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702b000 0x0 0x1000>; + interrupts = <0 67 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = < + &pmx0 0 74 6 + &pmx0 6 122 1 + &pmx0 7 126 1 + >; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio16: gpio@f702c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702c000 0x0 0x1000>; + interrupts = <0 68 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 127 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio17: gpio@f702d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702d000 0x0 0x1000>; + interrupts = <0 69 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 135 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio18: gpio@f702e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702e000 0x0 0x1000>; + interrupts = <0 70 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 143 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + gpio19: gpio@f702f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x0 0xf702f000 0x0 0x1000>; + interrupts = <0 71 0x4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pmx0 0 151 8>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&ao_ctrl 2>; + clock-names = "apb_pclk"; + }; + + spi0: spi@f7106000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xf7106000 0x0 0x1000>; + interrupts = <0 50 4>; + bus-id = <0>; + enable-dma = <0>; + clocks = <&sys_ctrl HI6220_SPI_CLK>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; + num-cs = <1>; + cs-gpios = <&gpio6 2 0>; + status = "disabled"; + }; + + i2c0: i2c@f7100000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xf7100000 0x0 0x1000>; + interrupts = <0 44 4>; + clocks = <&sys_ctrl HI6220_I2C0_CLK>; + i2c-sda-hold-time-ns = <300>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; + + i2c1: i2c@f7101000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xf7101000 0x0 0x1000>; + clocks = <&sys_ctrl HI6220_I2C1_CLK>; + interrupts = <0 45 4>; + i2c-sda-hold-time-ns = <300>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; + status = "disabled"; + }; + + i2c2: i2c@f7102000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xf7102000 0x0 0x1000>; + clocks = <&sys_ctrl HI6220_I2C2_CLK>; + interrupts = <0 46 4>; + i2c-sda-hold-time-ns = <300>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; + status = "disabled"; + }; + + usb_phy: usbphy { + compatible = "hisilicon,hi6220-usb-phy"; + #phy-cells = <0>; + phy-supply = <®_5v_hub>; + hisilicon,peripheral-syscon = <&sys_ctrl>; + }; + + usb: usb@f72c0000 { + compatible = "hisilicon,hi6220-usb"; + reg = <0x0 0xf72c0000 0x0 0x40000>; + phys = <&usb_phy>; + phy-names = "usb2-phy"; + clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; + clock-names = "otg"; + dr_mode = "otg"; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <128>; + g-tx-fifo-size = <128 128 128 128 128 128 128 128 + 16 16 16 16 16 16 16>; + interrupts = <0 77 0x4>; + }; + + mailbox: mailbox@f7510000 { + compatible = "hisilicon,hi6220-mbox"; + reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ + <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ + interrupts = ; + #mbox-cells = <3>; + }; + + dwmmc_0: dwmmc0@f723d000 { + compatible = "hisilicon,hi6220-dw-mshc"; + reg = <0x0 0xf723d000 0x0 0x1000>; + interrupts = <0x0 0x48 0x4>; + clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; + clock-names = "ciu", "biu"; + resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; + reset-names = "reset"; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func + &emmc_cfg_func &emmc_rst_cfg_func>; + }; + + dwmmc_1: dwmmc1@f723e000 { + compatible = "hisilicon,hi6220-dw-mshc"; + hisilicon,peripheral-syscon = <&ao_ctrl>; + reg = <0x0 0xf723e000 0x0 0x1000>; + interrupts = <0x0 0x49 0x4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; + clock-names = "ciu", "biu"; + resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; + reset-names = "reset"; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; + pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; + }; + + dwmmc_2: dwmmc2@f723f000 { + compatible = "hisilicon,hi6220-dw-mshc"; + reg = <0x0 0xf723f000 0x0 0x1000>; + interrupts = <0x0 0x4a 0x4>; + clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; + clock-names = "ciu", "biu"; + resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; + reset-names = "reset"; + pinctrl-names = "default", "idle"; + pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; + pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; + }; + + tsensor: tsensor@0,f7030700 { + compatible = "hisilicon,tsensor"; + reg = <0x0 0xf7030700 0x0 0x1000>; + interrupts = ; + clocks = <&sys_ctrl 22>; + clock-names = "thermal_clk"; + #thermal-sensor-cells = <1>; + }; + + i2s0: i2s@f7118000{ + compatible = "hisilicon,hi6210-i2s"; + reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */ + interrupts = ; /* 155 "DigACodec_intr"-32 */ + clocks = <&sys_ctrl HI6220_DACODEC_PCLK>, + <&sys_ctrl HI6220_BBPPLL0_DIV>; + clock-names = "dacodec", "i2s-base"; + dmas = <&dma0 15 &dma0 14>; + dma-names = "rx", "tx"; + hisilicon,sysctrl-syscon = <&sys_ctrl>; + #sound-dai-cells = <1>; + }; + + thermal-zones { + + cls0: cls0 { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <3326>; + + /* sensor ID */ + thermal-sensors = <&tsensor 2>; + + trips { + threshold: trip-point@0 { + temperature = <65000>; + hysteresis = <0>; + type = "passive"; + }; + + target: trip-point@1 { + temperature = <75000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + ade: ade@f4100000 { + compatible = "hisilicon,hi6220-ade"; + reg = <0x0 0xf4100000 0x0 0x7800>; + reg-names = "ade_base"; + hisilicon,noc-syscon = <&medianoc_ade>; + resets = <&media_ctrl MEDIA_ADE>; + interrupts = <0 115 4>; /* ldi interrupt */ + + clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>, + <&media_ctrl HI6220_ADE_PIX_SRC>; + /*clock name*/ + clock-names = "clk_ade_core", + "clk_codec_jpeg", + "clk_ade_pix"; + + assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>; + assigned-clock-rates = <360000000>, <288000000>; + dma-coherent; + status = "disabled"; + + port { + ade_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + + dsi: dsi@f4107800 { + compatible = "hisilicon,hi6220-dsi"; + reg = <0x0 0xf4107800 0x0 0x100>; + clocks = <&media_ctrl HI6220_DSI_PCLK>; + clock-names = "pclk"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* 0 for input port */ + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&ade_out>; + }; + }; + }; + }; + + debug@f6590000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; + + debug@f6592000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6592000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + }; + + debug@f6594000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6594000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + }; + + debug@f6596000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6596000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + }; + + debug@f65d0000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf65d0000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu4>; + }; + + debug@f65d2000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf65d2000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu5>; + }; + + debug@f65d4000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf65d4000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu6>; + }; + + debug@f65d6000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf65d6000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu7>; + }; + }; +}; + +#include "hi6220-coresight.dtsi" diff --git a/Platforms/Hisilicon/DeviceTree/hikey-pinctrl.dtsi b/Platforms/Hisilicon/DeviceTree/hikey-pinctrl.dtsi new file mode 100644 index 0000000..e7d2261 --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hikey-pinctrl.dtsi @@ -0,0 +1,706 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * pinctrl dts fils for Hislicon HiKey development board + * + */ +#include + +/ { + soc { + pmx0: pinmux@f7010000 { + pinctrl-names = "default"; + pinctrl-0 = < + &boot_sel_pmx_func + &hkadc_ssi_pmx_func + &codec_clk_pmx_func + &pwm_in_pmx_func + &bl_pwm_pmx_func + >; + + boot_sel_pmx_func: boot_sel_pmx_func { + pinctrl-single,pins = < + 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */ + >; + }; + + emmc_pmx_func: emmc_pmx_func { + pinctrl-single,pins = < + 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */ + 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */ + 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */ + 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */ + 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */ + 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */ + 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */ + 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */ + 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */ + 0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */ + >; + }; + + sd_pmx_func: sd_pmx_func { + pinctrl-single,pins = < + 0xc MUX_M0 /* SD_CLK (IOMG003) */ + 0x10 MUX_M0 /* SD_CMD (IOMG004) */ + 0x14 MUX_M0 /* SD_DATA0 (IOMG005) */ + 0x18 MUX_M0 /* SD_DATA1 (IOMG006) */ + 0x1c MUX_M0 /* SD_DATA2 (IOMG007) */ + 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */ + >; + }; + sd_pmx_idle: sd_pmx_idle { + pinctrl-single,pins = < + 0xc MUX_M1 /* SD_CLK (IOMG003) */ + 0x10 MUX_M1 /* SD_CMD (IOMG004) */ + 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */ + 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */ + 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */ + 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */ + >; + }; + + sdio_pmx_func: sdio_pmx_func { + pinctrl-single,pins = < + 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */ + 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */ + 0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */ + 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */ + 0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */ + 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */ + >; + }; + sdio_pmx_idle: sdio_pmx_idle { + pinctrl-single,pins = < + 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */ + 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */ + 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */ + 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */ + 0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */ + 0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */ + >; + }; + + isp_pmx_func: isp_pmx_func { + pinctrl-single,pins = < + 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */ + 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */ + 0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */ + 0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */ + 0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */ + 0x38 MUX_M1 /* ISP_PWM (IOMG014) */ + 0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */ + 0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */ + 0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */ + 0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */ + 0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */ + 0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */ + 0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */ + 0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */ + 0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */ + 0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */ + >; + }; + + hkadc_ssi_pmx_func: hkadc_ssi_pmx_func { + pinctrl-single,pins = < + 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */ + >; + }; + + codec_clk_pmx_func: codec_clk_pmx_func { + pinctrl-single,pins = < + 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */ + >; + }; + + codec_pmx_func: codec_pmx_func { + pinctrl-single,pins = < + 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */ + 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */ + 0x78 MUX_M0 /* CODEC_DI (IOMG030) */ + 0x7c MUX_M0 /* CODEC_DO (IOMG031) */ + >; + }; + + fm_pmx_func: fm_pmx_func { + pinctrl-single,pins = < + 0x80 MUX_M1 /* FM_XCLK (IOMG032) */ + 0x84 MUX_M1 /* FM_XFS (IOMG033) */ + 0x88 MUX_M1 /* FM_DI (IOMG034) */ + 0x8c MUX_M1 /* FM_DO (IOMG035) */ + >; + }; + + bt_pmx_func: bt_pmx_func { + pinctrl-single,pins = < + 0x90 MUX_M0 /* BT_XCLK (IOMG036) */ + 0x94 MUX_M0 /* BT_XFS (IOMG037) */ + 0x98 MUX_M0 /* BT_DI (IOMG038) */ + 0x9c MUX_M0 /* BT_DO (IOMG039) */ + >; + }; + + pwm_in_pmx_func: pwm_in_pmx_func { + pinctrl-single,pins = < + 0xb8 MUX_M1 /* PWM_IN (IOMG046) */ + >; + }; + + bl_pwm_pmx_func: bl_pwm_pmx_func { + pinctrl-single,pins = < + 0xbc MUX_M1 /* BL_PWM (IOMG047) */ + >; + }; + + uart0_pmx_func: uart0_pmx_func { + pinctrl-single,pins = < + 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */ + 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */ + >; + }; + + uart1_pmx_func: uart1_pmx_func { + pinctrl-single,pins = < + 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */ + 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */ + 0xd0 MUX_M0 /* UART1_RXD (IOMG052) */ + 0xd4 MUX_M0 /* UART1_TXD (IOMG053) */ + >; + }; + + uart2_pmx_func: uart2_pmx_func { + pinctrl-single,pins = < + 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */ + 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */ + 0xe0 MUX_M0 /* UART2_RXD (IOMG056) */ + 0xe4 MUX_M0 /* UART2_TXD (IOMG057) */ + >; + }; + + uart3_pmx_func: uart3_pmx_func { + pinctrl-single,pins = < + 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */ + 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */ + 0x188 MUX_M1 /* UART3_RXD (IOMG098) */ + 0x18c MUX_M1 /* UART3_TXD (IOMG099) */ + >; + }; + + uart4_pmx_func: uart4_pmx_func { + pinctrl-single,pins = < + 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */ + 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */ + 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */ + 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */ + >; + }; + + uart5_pmx_func: uart5_pmx_func { + pinctrl-single,pins = < + 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */ + 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */ + >; + }; + + i2c0_pmx_func: i2c0_pmx_func { + pinctrl-single,pins = < + 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */ + 0xec MUX_M0 /* I2C0_SDA (IOMG059) */ + >; + }; + + i2c1_pmx_func: i2c1_pmx_func { + pinctrl-single,pins = < + 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */ + 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */ + >; + }; + + i2c2_pmx_func: i2c2_pmx_func { + pinctrl-single,pins = < + 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */ + 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */ + >; + }; + + spi0_pmx_func: spi0_pmx_func { + pinctrl-single,pins = < + 0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */ + 0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */ + 0x1a8 MUX_M1 /* SPI0_CS_N (IOMG106) */ + 0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */ + >; + }; + }; + + pmx1: pinmux@f7010800 { + + pinctrl-names = "default"; + pinctrl-0 = < + &boot_sel_cfg_func + &hkadc_ssi_cfg_func + &codec_clk_cfg_func + &pwm_in_cfg_func + &bl_pwm_cfg_func + >; + + boot_sel_cfg_func: boot_sel_cfg_func { + pinctrl-single,pins = < + 0x0 0x0 /* BOOT_SEL (IOCFG000) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + hkadc_ssi_cfg_func: hkadc_ssi_cfg_func { + pinctrl-single,pins = < + 0x6c 0x0 /* HKADC_SSI (IOCFG027) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + emmc_clk_cfg_func: emmc_clk_cfg_func { + pinctrl-single,pins = < + 0x104 0x0 /* EMMC_CLK (IOCFG065) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + emmc_cfg_func: emmc_cfg_func { + pinctrl-single,pins = < + 0x108 0x0 /* EMMC_CMD (IOCFG066) */ + 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */ + 0x110 0x0 /* EMMC_DATA1 (IOCFG068) */ + 0x114 0x0 /* EMMC_DATA2 (IOCFG069) */ + 0x118 0x0 /* EMMC_DATA3 (IOCFG070) */ + 0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */ + 0x120 0x0 /* EMMC_DATA5 (IOCFG072) */ + 0x124 0x0 /* EMMC_DATA6 (IOCFG073) */ + 0x128 0x0 /* EMMC_DATA7 (IOCFG074) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + emmc_rst_cfg_func: emmc_rst_cfg_func { + pinctrl-single,pins = < + 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + sd_clk_cfg_func: sd_clk_cfg_func { + pinctrl-single,pins = < + 0xc 0x0 /* SD_CLK (IOCFG003) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + sd_clk_cfg_idle: sd_clk_cfg_idle { + pinctrl-single,pins = < + 0xc 0x0 /* SD_CLK (IOCFG003) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + sd_cfg_func: sd_cfg_func { + pinctrl-single,pins = < + 0x10 0x0 /* SD_CMD (IOCFG004) */ + 0x14 0x0 /* SD_DATA0 (IOCFG005) */ + 0x18 0x0 /* SD_DATA1 (IOCFG006) */ + 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ + 0x20 0x0 /* SD_DATA3 (IOCFG008) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + sd_cfg_idle: sd_cfg_idle { + pinctrl-single,pins = < + 0x10 0x0 /* SD_CMD (IOCFG004) */ + 0x14 0x0 /* SD_DATA0 (IOCFG005) */ + 0x18 0x0 /* SD_DATA1 (IOCFG006) */ + 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ + 0x20 0x0 /* SD_DATA3 (IOCFG008) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + sdio_clk_cfg_func: sdio_clk_cfg_func { + pinctrl-single,pins = < + 0x134 0x0 /* SDIO_CLK (IOCFG077) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + sdio_clk_cfg_idle: sdio_clk_cfg_idle { + pinctrl-single,pins = < + 0x134 0x0 /* SDIO_CLK (IOCFG077) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + sdio_cfg_func: sdio_cfg_func { + pinctrl-single,pins = < + 0x138 0x0 /* SDIO_CMD (IOCFG078) */ + 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ + 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ + 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ + 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + sdio_cfg_idle: sdio_cfg_idle { + pinctrl-single,pins = < + 0x138 0x0 /* SDIO_CMD (IOCFG078) */ + 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ + 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ + 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ + 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + isp_cfg_func1: isp_cfg_func1 { + pinctrl-single,pins = < + 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */ + 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */ + 0x30 0x0 /* ISP_PWDN2 (IOCFG012) */ + 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ + 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ + 0x3c 0x0 /* ISP_PWM (IOCFG015) */ + 0x40 0x0 /* ISP_CCLK0 (IOCFG016) */ + 0x44 0x0 /* ISP_CCLK1 (IOCFG017) */ + 0x48 0x0 /* ISP_RESETB0 (IOCFG018) */ + 0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */ + 0x50 0x0 /* ISP_STROBE0 (IOCFG020) */ + 0x58 0x0 /* ISP_SDA0 (IOCFG022) */ + 0x5c 0x0 /* ISP_SCL0 (IOCFG023) */ + 0x60 0x0 /* ISP_SDA1 (IOCFG024) */ + 0x64 0x0 /* ISP_SCL1 (IOCFG025) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + isp_cfg_idle1: isp_cfg_idle1 { + pinctrl-single,pins = < + 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ + 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + isp_cfg_func2: isp_cfg_func2 { + pinctrl-single,pins = < + 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + codec_clk_cfg_func: codec_clk_cfg_func { + pinctrl-single,pins = < + 0x70 0x0 /* CODEC_CLK (IOCFG028) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + codec_clk_cfg_idle: codec_clk_cfg_idle { + pinctrl-single,pins = < + 0x70 0x0 /* CODEC_CLK (IOCFG028) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + codec_cfg_func1: codec_cfg_func1 { + pinctrl-single,pins = < + 0x74 0x0 /* DMIC_CLK (IOCFG029) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + codec_cfg_func2: codec_cfg_func2 { + pinctrl-single,pins = < + 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ + 0x7c 0x0 /* CODEC_DI (IOCFG031) */ + 0x80 0x0 /* CODEC_DO (IOCFG032) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + codec_cfg_idle2: codec_cfg_idle2 { + pinctrl-single,pins = < + 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ + 0x7c 0x0 /* CODEC_DI (IOCFG031) */ + 0x80 0x0 /* CODEC_DO (IOCFG032) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + fm_cfg_func: fm_cfg_func { + pinctrl-single,pins = < + 0x84 0x0 /* FM_XCLK (IOCFG033) */ + 0x88 0x0 /* FM_XFS (IOCFG034) */ + 0x8c 0x0 /* FM_DI (IOCFG035) */ + 0x90 0x0 /* FM_DO (IOCFG036) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + bt_cfg_func: bt_cfg_func { + pinctrl-single,pins = < + 0x94 0x0 /* BT_XCLK (IOCFG037) */ + 0x98 0x0 /* BT_XFS (IOCFG038) */ + 0x9c 0x0 /* BT_DI (IOCFG039) */ + 0xa0 0x0 /* BT_DO (IOCFG040) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + bt_cfg_idle: bt_cfg_idle { + pinctrl-single,pins = < + 0x94 0x0 /* BT_XCLK (IOCFG037) */ + 0x98 0x0 /* BT_XFS (IOCFG038) */ + 0x9c 0x0 /* BT_DI (IOCFG039) */ + 0xa0 0x0 /* BT_DO (IOCFG040) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + pwm_in_cfg_func: pwm_in_cfg_func { + pinctrl-single,pins = < + 0xbc 0x0 /* PWM_IN (IOCFG047) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + bl_pwm_cfg_func: bl_pwm_cfg_func { + pinctrl-single,pins = < + 0xc0 0x0 /* BL_PWM (IOCFG048) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart0_cfg_func1: uart0_cfg_func1 { + pinctrl-single,pins = < + 0xc4 0x0 /* UART0_RXD (IOCFG049) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart0_cfg_func2: uart0_cfg_func2 { + pinctrl-single,pins = < + 0xc8 0x0 /* UART0_TXD (IOCFG050) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart1_cfg_func1: uart1_cfg_func1 { + pinctrl-single,pins = < + 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */ + 0xd4 0x0 /* UART1_RXD (IOCFG053) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart1_cfg_func2: uart1_cfg_func2 { + pinctrl-single,pins = < + 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */ + 0xd8 0x0 /* UART1_TXD (IOCFG054) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart2_cfg_func: uart2_cfg_func { + pinctrl-single,pins = < + 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */ + 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */ + 0xe4 0x0 /* UART2_RXD (IOCFG057) */ + 0xe8 0x0 /* UART2_TXD (IOCFG058) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart3_cfg_func: uart3_cfg_func { + pinctrl-single,pins = < + 0x190 0x0 /* UART3_CTS_N (IOCFG100) */ + 0x194 0x0 /* UART3_RTS_N (IOCFG101) */ + 0x198 0x0 /* UART3_RXD (IOCFG102) */ + 0x19c 0x0 /* UART3_TXD (IOCFG103) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart4_cfg_func: uart4_cfg_func { + pinctrl-single,pins = < + 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */ + 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */ + 0x1e8 0x0 /* UART4_RXD (IOCFG122) */ + 0x1ec 0x0 /* UART4_TXD (IOCFG123) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + uart5_cfg_func: uart5_cfg_func { + pinctrl-single,pins = < + 0x1d8 0x0 /* UART4_RXD (IOCFG118) */ + 0x1dc 0x0 /* UART4_TXD (IOCFG119) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + i2c0_cfg_func: i2c0_cfg_func { + pinctrl-single,pins = < + 0xec 0x0 /* I2C0_SCL (IOCFG059) */ + 0xf0 0x0 /* I2C0_SDA (IOCFG060) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + i2c1_cfg_func: i2c1_cfg_func { + pinctrl-single,pins = < + 0xf4 0x0 /* I2C1_SCL (IOCFG061) */ + 0xf8 0x0 /* I2C1_SDA (IOCFG062) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + i2c2_cfg_func: i2c2_cfg_func { + pinctrl-single,pins = < + 0xfc 0x0 /* I2C2_SCL (IOCFG063) */ + 0x100 0x0 /* I2C2_SDA (IOCFG064) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + spi0_cfg_func: spi0_cfg_func { + pinctrl-single,pins = < + 0x1b0 0x0 /* SPI0_DI (IOCFG108) */ + 0x1b4 0x0 /* SPI0_DO (IOCFG109) */ + 0x1b8 0x0 /* SPI0_CS_N (IOCFG110) */ + 0x1bc 0x0 /* SPI0_CLK (IOCFG111) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + }; + + pmx2: pinmux@f8001800 { + + pinctrl-names = "default"; + pinctrl-0 = < + &rstout_n_cfg_func + >; + + rstout_n_cfg_func: rstout_n_cfg_func { + pinctrl-single,pins = < + 0x0 0x0 /* RSTOUT_N (IOCFG000) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + pmu_peri_en_cfg_func: pmu_peri_en_cfg_func { + pinctrl-single,pins = < + 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + sysclk0_en_cfg_func: sysclk0_en_cfg_func { + pinctrl-single,pins = < + 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + jtag_tdo_cfg_func: jtag_tdo_cfg_func { + pinctrl-single,pins = < + 0xc 0x0 /* JTAG_TDO (IOCFG003) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + + rf_reset_cfg_func: rf_reset_cfg_func { + pinctrl-single,pins = < + 0x70 0x0 /* RF_RESET0 (IOCFG028) */ + 0x74 0x0 /* RF_RESET1 (IOCFG029) */ + >; + pinctrl-single,bias-pulldown = ; + pinctrl-single,bias-pullup = ; + pinctrl-single,drive-strength = ; + }; + }; + }; +}; diff --git a/Platforms/Hisilicon/DeviceTree/hikey960-pinctrl.dtsi b/Platforms/Hisilicon/DeviceTree/hikey960-pinctrl.dtsi new file mode 100644 index 0000000..d11efc8 --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hikey960-pinctrl.dtsi @@ -0,0 +1,1060 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * pinctrl dts fils for Hislicon HiKey960 development board + * + */ + +#include + +/ { + soc { + /* [IOMG_000, IOMG_123] */ + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + + pmx0: pinmux@e896c000 { + compatible = "pinctrl-single"; + reg = <0x0 0xe896c000 0x0 0x1f0>; + #pinctrl-cells = <1>; + #gpio-range-cells = <0x3>; + pinctrl-single,register-width = <0x20>; + pinctrl-single,function-mask = <0x7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = < + &range 0 7 0 + &range 8 116 0>; + + pmu_pmx_func: pmu_pmx_func { + pinctrl-single,pins = < + 0x008 MUX_M1 /* PMU1_SSI */ + 0x00c MUX_M1 /* PMU2_SSI */ + 0x010 MUX_M1 /* PMU_CLKOUT */ + 0x100 MUX_M1 /* PMU_HKADC_SSI */ + >; + }; + + csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x044 MUX_M0 /* CSI0_PWD_N */ + >; + }; + + csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x04c MUX_M0 /* CSI1_PWD_N */ + >; + }; + + isp0_pmx_func: isp0_pmx_func { + pinctrl-single,pins = < + 0x058 MUX_M1 /* ISP_CLK0 */ + 0x064 MUX_M1 /* ISP_SCL0 */ + 0x068 MUX_M1 /* ISP_SDA0 */ + >; + }; + + isp1_pmx_func: isp1_pmx_func { + pinctrl-single,pins = < + 0x05c MUX_M1 /* ISP_CLK1 */ + 0x06c MUX_M1 /* ISP_SCL1 */ + 0x070 MUX_M1 /* ISP_SDA1 */ + >; + }; + + pwr_key_pmx_func: pwr_key_pmx_func { + pinctrl-single,pins = < + 0x080 MUX_M0 /* GPIO_034 */ + >; + }; + + i2c3_pmx_func: i2c3_pmx_func { + pinctrl-single,pins = < + 0x02c MUX_M1 /* I2C3_SCL */ + 0x030 MUX_M1 /* I2C3_SDA */ + >; + }; + + i2c4_pmx_func: i2c4_pmx_func { + pinctrl-single,pins = < + 0x090 MUX_M1 /* I2C4_SCL */ + 0x094 MUX_M1 /* I2C4_SDA */ + >; + }; + + pcie_perstn_pmx_func: pcie_perstn_pmx_func { + pinctrl-single,pins = < + 0x15c MUX_M1 /* PCIE_PERST_N */ + >; + }; + + usbhub5734_pmx_func: usbhub5734_pmx_func { + pinctrl-single,pins = < + 0x11c MUX_M0 /* GPIO_073 */ + 0x120 MUX_M0 /* GPIO_074 */ + >; + }; + + uart0_pmx_func: uart0_pmx_func { + pinctrl-single,pins = < + 0x0cc MUX_M2 /* UART0_RXD */ + 0x0d0 MUX_M2 /* UART0_TXD */ + >; + }; + + uart1_pmx_func: uart1_pmx_func { + pinctrl-single,pins = < + 0x0b0 MUX_M2 /* UART1_CTS_N */ + 0x0b4 MUX_M2 /* UART1_RTS_N */ + 0x0a8 MUX_M2 /* UART1_RXD */ + 0x0ac MUX_M2 /* UART1_TXD */ + >; + }; + + uart2_pmx_func: uart2_pmx_func { + pinctrl-single,pins = < + 0x0bc MUX_M2 /* UART2_CTS_N */ + 0x0c0 MUX_M2 /* UART2_RTS_N */ + 0x0c8 MUX_M2 /* UART2_RXD */ + 0x0c4 MUX_M2 /* UART2_TXD */ + >; + }; + + uart3_pmx_func: uart3_pmx_func { + pinctrl-single,pins = < + 0x0dc MUX_M1 /* UART3_CTS_N */ + 0x0e0 MUX_M1 /* UART3_RTS_N */ + 0x0e4 MUX_M1 /* UART3_RXD */ + 0x0e8 MUX_M1 /* UART3_TXD */ + >; + }; + + uart4_pmx_func: uart4_pmx_func { + pinctrl-single,pins = < + 0x0ec MUX_M1 /* UART4_CTS_N */ + 0x0f0 MUX_M1 /* UART4_RTS_N */ + 0x0f4 MUX_M1 /* UART4_RXD */ + 0x0f8 MUX_M1 /* UART4_TXD */ + >; + }; + + uart5_pmx_func: uart5_pmx_func { + pinctrl-single,pins = < + 0x0c4 MUX_M3 /* UART5_CTS_N */ + 0x0c8 MUX_M3 /* UART5_RTS_N */ + 0x0bc MUX_M3 /* UART5_RXD */ + 0x0c0 MUX_M3 /* UART5_TXD */ + >; + }; + + uart6_pmx_func: uart6_pmx_func { + pinctrl-single,pins = < + 0x0cc MUX_M1 /* UART6_CTS_N */ + 0x0d0 MUX_M1 /* UART6_RTS_N */ + 0x0d4 MUX_M1 /* UART6_RXD */ + 0x0d8 MUX_M1 /* UART6_TXD */ + >; + }; + + cam0_rst_pmx_func: cam0_rst_pmx_func { + pinctrl-single,pins = < + 0x0c8 MUX_M0 /* CAM0_RST */ + >; + }; + + cam1_rst_pmx_func: cam1_rst_pmx_func { + pinctrl-single,pins = < + 0x124 MUX_M0 /* CAM1_RST */ + >; + }; + }; + + /* [IOMG_MMC0_000, IOMG_MMC0_005] */ + pmx1: pinmux@ff37e000 { + compatible = "pinctrl-single"; + reg = <0x0 0xff37e000 0x0 0x18>; + #gpio-range-cells = <0x3>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + pinctrl-single,function-mask = <0x7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 6 0>; + + sd_pmx_func: sd_pmx_func { + pinctrl-single,pins = < + 0x000 MUX_M1 /* SD_CLK */ + 0x004 MUX_M1 /* SD_CMD */ + 0x008 MUX_M1 /* SD_DATA0 */ + 0x00c MUX_M1 /* SD_DATA1 */ + 0x010 MUX_M1 /* SD_DATA2 */ + 0x014 MUX_M1 /* SD_DATA3 */ + >; + }; + }; + + /* [IOMG_FIX_000, IOMG_FIX_011] */ + pmx2: pinmux@ff3b6000 { + compatible = "pinctrl-single"; + reg = <0x0 0xff3b6000 0x0 0x30>; + #pinctrl-cells = <1>; + #gpio-range-cells = <0x3>; + pinctrl-single,register-width = <0x20>; + pinctrl-single,function-mask = <0x7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 12 0>; + + ufs_pmx_func: ufs_pmx_func { + pinctrl-single,pins = < + 0x000 MUX_M1 /* UFS_REF_CLK */ + 0x004 MUX_M1 /* UFS_RST_N */ + >; + }; + + spi3_pmx_func: spi3_pmx_func { + pinctrl-single,pins = < + 0x008 MUX_M1 /* SPI3_CLK */ + 0x00c MUX_M1 /* SPI3_DI */ + 0x010 MUX_M1 /* SPI3_DO */ + 0x014 MUX_M1 /* SPI3_CS0_N */ + >; + }; + }; + + /* [IOMG_MMC1_000, IOMG_MMC1_005] */ + pmx3: pinmux@ff3fd000 { + compatible = "pinctrl-single"; + reg = <0x0 0xff3fd000 0x0 0x18>; + #pinctrl-cells = <1>; + #gpio-range-cells = <0x3>; + pinctrl-single,register-width = <0x20>; + pinctrl-single,function-mask = <0x7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 6 0>; + + sdio_pmx_func: sdio_pmx_func { + pinctrl-single,pins = < + 0x000 MUX_M1 /* SDIO_CLK */ + 0x004 MUX_M1 /* SDIO_CMD */ + 0x008 MUX_M1 /* SDIO_DATA0 */ + 0x00c MUX_M1 /* SDIO_DATA1 */ + 0x010 MUX_M1 /* SDIO_DATA2 */ + 0x014 MUX_M1 /* SDIO_DATA3 */ + >; + }; + }; + + /* [IOMG_AO_000, IOMG_AO_041] */ + pmx4: pinmux@fff11000 { + compatible = "pinctrl-single"; + reg = <0x0 0xfff11000 0x0 0xa8>; + #pinctrl-cells = <1>; + #gpio-range-cells = <0x3>; + pinctrl-single,register-width = <0x20>; + pinctrl-single,function-mask = <0x7>; + /* pin base in node, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 42 0>; + + i2s2_pmx_func: i2s2_pmx_func { + pinctrl-single,pins = < + 0x044 MUX_M1 /* I2S2_DI */ + 0x048 MUX_M1 /* I2S2_DO */ + 0x04c MUX_M1 /* I2S2_XCLK */ + 0x050 MUX_M1 /* I2S2_XFS */ + >; + }; + + slimbus_pmx_func: slimbus_pmx_func { + pinctrl-single,pins = < + 0x02c MUX_M1 /* SLIMBUS_CLK */ + 0x030 MUX_M1 /* SLIMBUS_DATA */ + >; + }; + + i2c0_pmx_func: i2c0_pmx_func { + pinctrl-single,pins = < + 0x014 MUX_M1 /* I2C0_SCL */ + 0x018 MUX_M1 /* I2C0_SDA */ + >; + }; + + i2c1_pmx_func: i2c1_pmx_func { + pinctrl-single,pins = < + 0x01c MUX_M1 /* I2C1_SCL */ + 0x020 MUX_M1 /* I2C1_SDA */ + >; + }; + + i2c7_pmx_func: i2c7_pmx_func { + pinctrl-single,pins = < + 0x024 MUX_M3 /* I2C7_SCL */ + 0x028 MUX_M3 /* I2C7_SDA */ + >; + }; + + pcie_pmx_func: pcie_pmx_func { + pinctrl-single,pins = < + 0x084 MUX_M1 /* PCIE_CLKREQ_N */ + 0x088 MUX_M1 /* PCIE_WAKE_N */ + >; + }; + + spi2_pmx_func: spi2_pmx_func { + pinctrl-single,pins = < + 0x08c MUX_M1 /* SPI2_CLK */ + 0x090 MUX_M1 /* SPI2_DI */ + 0x094 MUX_M1 /* SPI2_DO */ + 0x098 MUX_M1 /* SPI2_CS0_N */ + >; + }; + + i2s0_pmx_func: i2s0_pmx_func { + pinctrl-single,pins = < + 0x034 MUX_M1 /* I2S0_DI */ + 0x038 MUX_M1 /* I2S0_DO */ + 0x03c MUX_M1 /* I2S0_XCLK */ + 0x040 MUX_M1 /* I2S0_XFS */ + >; + }; + }; + + pmx5: pinmux@e896c800 { + compatible = "pinconf-single"; + reg = <0x0 0xe896c800 0x0 0x200>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + pmu_cfg_func: pmu_cfg_func { + pinctrl-single,pins = < + 0x010 0x0 /* PMU1_SSI */ + 0x014 0x0 /* PMU2_SSI */ + 0x018 0x0 /* PMU_CLKOUT */ + 0x10c 0x0 /* PMU_HKADC_SSI */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_06MA DRIVE6_MASK + >; + }; + + i2c3_cfg_func: i2c3_cfg_func { + pinctrl-single,pins = < + 0x038 0x0 /* I2C3_SCL */ + 0x03c 0x0 /* I2C3_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x050 0x0 /* CSI0_PWD_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x058 0x0 /* CSI1_PWD_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + isp0_cfg_func: isp0_cfg_func { + pinctrl-single,pins = < + 0x064 0x0 /* ISP_CLK0 */ + 0x070 0x0 /* ISP_SCL0 */ + 0x074 0x0 /* ISP_SDA0 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK>; + }; + + isp1_cfg_func: isp1_cfg_func { + pinctrl-single,pins = < + 0x068 0x0 /* ISP_CLK1 */ + 0x078 0x0 /* ISP_SCL1 */ + 0x07c 0x0 /* ISP_SDA1 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + pwr_key_cfg_func: pwr_key_cfg_func { + pinctrl-single,pins = < + 0x08c 0x0 /* GPIO_034 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart1_cfg_func: uart1_cfg_func { + pinctrl-single,pins = < + 0x0b4 0x0 /* UART1_RXD */ + 0x0b8 0x0 /* UART1_TXD */ + 0x0bc 0x0 /* UART1_CTS_N */ + 0x0c0 0x0 /* UART1_RTS_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart2_cfg_func: uart2_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* UART2_CTS_N */ + 0x0cc 0x0 /* UART2_RTS_N */ + 0x0d0 0x0 /* UART2_TXD */ + 0x0d4 0x0 /* UART2_RXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart5_cfg_func: uart5_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* UART5_RXD */ + 0x0cc 0x0 /* UART5_TXD */ + 0x0d0 0x0 /* UART5_CTS_N */ + 0x0d4 0x0 /* UART5_RTS_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + cam0_rst_cfg_func: cam0_rst_cfg_func { + pinctrl-single,pins = < + 0x0d4 0x0 /* CAM0_RST */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart0_cfg_func: uart0_cfg_func { + pinctrl-single,pins = < + 0x0d8 0x0 /* UART0_RXD */ + 0x0dc 0x0 /* UART0_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart6_cfg_func: uart6_cfg_func { + pinctrl-single,pins = < + 0x0d8 0x0 /* UART6_CTS_N */ + 0x0dc 0x0 /* UART6_RTS_N */ + 0x0e0 0x0 /* UART6_RXD */ + 0x0e4 0x0 /* UART6_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart3_cfg_func: uart3_cfg_func { + pinctrl-single,pins = < + 0x0e8 0x0 /* UART3_CTS_N */ + 0x0ec 0x0 /* UART3_RTS_N */ + 0x0f0 0x0 /* UART3_RXD */ + 0x0f4 0x0 /* UART3_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart4_cfg_func: uart4_cfg_func { + pinctrl-single,pins = < + 0x0f8 0x0 /* UART4_CTS_N */ + 0x0fc 0x0 /* UART4_RTS_N */ + 0x100 0x0 /* UART4_RXD */ + 0x104 0x0 /* UART4_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + cam1_rst_cfg_func: cam1_rst_cfg_func { + pinctrl-single,pins = < + 0x130 0x0 /* CAM1_RST */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + }; + + pmx6: pinmux@ff3b6800 { + compatible = "pinconf-single"; + reg = <0x0 0xff3b6800 0x0 0x18>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + ufs_cfg_func: ufs_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* UFS_REF_CLK */ + 0x004 0x0 /* UFS_RST_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_08MA DRIVE6_MASK + >; + }; + + spi3_cfg_func: spi3_cfg_func { + pinctrl-single,pins = < + 0x008 0x0 /* SPI3_CLK */ + 0x0 /* SPI3_DI */ + 0x010 0x0 /* SPI3_DO */ + 0x014 0x0 /* SPI3_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + }; + + pmx7: pinmux@ff3fd800 { + compatible = "pinconf-single"; + reg = <0x0 0xff3fd800 0x0 0x18>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + sdio_clk_cfg_func: sdio_clk_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* SDIO_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_32MA DRIVE6_MASK + >; + }; + + sdio_cfg_func: sdio_cfg_func { + pinctrl-single,pins = < + 0x004 0x0 /* SDIO_CMD */ + 0x008 0x0 /* SDIO_DATA0 */ + 0x00c 0x0 /* SDIO_DATA1 */ + 0x010 0x0 /* SDIO_DATA2 */ + 0x014 0x0 /* SDIO_DATA3 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_19MA DRIVE6_MASK + >; + }; + }; + + pmx8: pinmux@ff37e800 { + compatible = "pinconf-single"; + reg = <0x0 0xff37e800 0x0 0x18>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + sd_clk_cfg_func: sd_clk_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* SD_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_32MA + DRIVE6_MASK + >; + }; + + sd_cfg_func: sd_cfg_func { + pinctrl-single,pins = < + 0x004 0x0 /* SD_CMD */ + 0x008 0x0 /* SD_DATA0 */ + 0x00c 0x0 /* SD_DATA1 */ + 0x010 0x0 /* SD_DATA2 */ + 0x014 0x0 /* SD_DATA3 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_19MA + DRIVE6_MASK + >; + }; + }; + + pmx9: pinmux@fff11800 { + compatible = "pinconf-single"; + reg = <0x0 0xfff11800 0x0 0xbc>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + i2c0_cfg_func: i2c0_cfg_func { + pinctrl-single,pins = < + 0x01c 0x0 /* I2C0_SCL */ + 0x020 0x0 /* I2C0_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2c1_cfg_func: i2c1_cfg_func { + pinctrl-single,pins = < + 0x024 0x0 /* I2C1_SCL */ + 0x028 0x0 /* I2C1_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2c7_cfg_func: i2c7_cfg_func { + pinctrl-single,pins = < + 0x02c 0x0 /* I2C7_SCL */ + 0x030 0x0 /* I2C7_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + slimbus_cfg_func: slimbus_cfg_func { + pinctrl-single,pins = < + 0x034 0x0 /* SLIMBUS_CLK */ + 0x038 0x0 /* SLIMBUS_DATA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2s0_cfg_func: i2s0_cfg_func { + pinctrl-single,pins = < + 0x040 0x0 /* I2S0_DI */ + 0x044 0x0 /* I2S0_DO */ + 0x048 0x0 /* I2S0_XCLK */ + 0x04c 0x0 /* I2S0_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2s2_cfg_func: i2s2_cfg_func { + pinctrl-single,pins = < + 0x050 0x0 /* I2S2_DI */ + 0x054 0x0 /* I2S2_DO */ + 0x058 0x0 /* I2S2_XCLK */ + 0x05c 0x0 /* I2S2_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + pcie_cfg_func: pcie_cfg_func { + pinctrl-single,pins = < + 0x094 0x0 /* PCIE_CLKREQ_N */ + 0x098 0x0 /* PCIE_WAKE_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + spi2_cfg_func: spi2_cfg_func { + pinctrl-single,pins = < + 0x09c 0x0 /* SPI2_CLK */ + 0x0a0 0x0 /* SPI2_DI */ + 0x0a4 0x0 /* SPI2_DO */ + 0x0a8 0x0 /* SPI2_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + usb_cfg_func: usb_cfg_func { + pinctrl-single,pins = < + 0x0ac 0x0 /* GPIO_219 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + }; + }; +}; diff --git a/Platforms/Hisilicon/DeviceTree/hip05-d02.dtb b/Platforms/Hisilicon/DeviceTree/hip05-d02.dtb new file mode 100644 index 0000000..d90d915 Binary files /dev/null and b/Platforms/Hisilicon/DeviceTree/hip05-d02.dtb differ diff --git a/Platforms/Hisilicon/DeviceTree/hip05-d02.dts b/Platforms/Hisilicon/DeviceTree/hip05-d02.dts new file mode 100644 index 0000000..3bbd017 --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hip05-d02.dts @@ -0,0 +1,88 @@ +/** + * dts file for Hisilicon D02 Development Board + * + * Copyright (C) 2014,2015 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +/dts-v1/; + +#include +#include "hip05.dtsi" + +/ { + model = "Hisilicon Hip05 D02 Development Board"; + compatible = "hisilicon,hip05-d02"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x80000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + pwrbutton { + label = "Power Button"; + gpios = <&porta 8 GPIO_ACTIVE_LOW>; + linux,code = <116>; + debounce-interval = <0>; + }; + }; +}; + +&uart0 { + status = "ok"; +}; + +&peri_gpio0 { + status = "ok"; +}; + +&lbc { + status = "ok"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x90000000 0x08000000>, + <1 0 0x0 0x98000000 0x08000000>; + + nor-flash@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "numonyx,js28f00a", "cfi-flash"; + reg = <0 0x0 0x08000000>; + bank-width = <2>; + /* The three parts may not used */ + partition@0 { + label = "BIOS"; + reg = <0x0 0x300000>; + }; + partition@300000 { + label = "Linux"; + reg = <0x300000 0xa00000>; + }; + partition@1000000 { + label = "Rootfs"; + reg = <0x01000000 0x02000000>; + }; + }; + + cpld@1,0 { + compatible = "hisilicon,hip05-cpld"; + reg = <1 0x0 0x100>; + }; +}; diff --git a/Platforms/Hisilicon/DeviceTree/hip05.dtsi b/Platforms/Hisilicon/DeviceTree/hip05.dtsi new file mode 100644 index 0000000..4b472a3 --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hip05.dtsi @@ -0,0 +1,369 @@ +/** + * dts file for Hisilicon D02 Development Board + * + * Copyright (C) 2014,2015 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +#include + +/ { + compatible = "hisilicon,hip05-d02"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu8>; + }; + core1 { + cpu = <&cpu9>; + }; + core2 { + cpu = <&cpu10>; + }; + core3 { + cpu = <&cpu11>; + }; + }; + cluster3 { + core0 { + cpu = <&cpu12>; + }; + core1 { + cpu = <&cpu13>; + }; + core2 { + cpu = <&cpu14>; + }; + core3 { + cpu = <&cpu15>; + }; + }; + }; + + cpu0: cpu@20000 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20000>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu1: cpu@20001 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20001>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu2: cpu@20002 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20002>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu3: cpu@20003 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20003>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu4: cpu@20100 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20100>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu5: cpu@20101 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20101>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu6: cpu@20102 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20102>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu7: cpu@20103 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20103>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu8: cpu@20200 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20200>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + }; + + cpu9: cpu@20201 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20201>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + }; + + cpu10: cpu@20202 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20202>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + }; + + cpu11: cpu@20203 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20203>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + }; + + cpu12: cpu@20300 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20300>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cpu13: cpu@20301 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20301>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cpu14: cpu@20302 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20302>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cpu15: cpu@20303 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x20303>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + }; + + cluster2_l2: l2-cache2 { + compatible = "cache"; + }; + + cluster3_l2: l2-cache3 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@8d000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x30000>; + reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ + <0x0 0x8d100000 0 0x300000>, /* GICR */ + <0x0 0xfe000000 0 0x10000>, /* GICC */ + <0x0 0xfe010000 0 0x10000>, /* GICH */ + <0x0 0xfe020000 0 0x10000>; /* GICV */ + interrupts = ; + + its_peri: interrupt-controller@8c000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x8c000000 0x0 0x40000>; + }; + + its_m3: interrupt-controller@a3000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xa3000000 0x0 0x40000>; + }; + + its_pcie: interrupt-controller@b7000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xb7000000 0x0 0x40000>; + }; + + its_dsa: interrupt-controller@c6000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xc6000000 0x0 0x40000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a57-pmu"; + interrupts = ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + refclk200mhz: refclk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart0: uart@80300000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x80300000 0x0 0x10000>; + interrupts = ; + clocks = <&refclk200mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: uart@80310000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x80310000 0x0 0x10000>; + interrupts = ; + clocks = <&refclk200mhz>; + clock-names = "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + lbc: localbus@80380000 { + compatible = "hisilicon,hisi-localbus", "simple-bus"; + reg = <0x0 0x80380000 0x0 0x10000>; + status = "disabled"; + }; + + peri_gpio0: gpio@802e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x802e0000 0x0 0x10000>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + peri_gpio1: gpio@802f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x802f0000 0x0 0x10000>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + }; +}; diff --git a/Platforms/Hisilicon/DeviceTree/hip06-d03.dtb b/Platforms/Hisilicon/DeviceTree/hip06-d03.dtb new file mode 100644 index 0000000..ea3018e Binary files /dev/null and b/Platforms/Hisilicon/DeviceTree/hip06-d03.dtb differ diff --git a/Platforms/Hisilicon/DeviceTree/hip06-d03.dts b/Platforms/Hisilicon/DeviceTree/hip06-d03.dts new file mode 100644 index 0000000..9af6330 --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hip06-d03.dts @@ -0,0 +1,54 @@ +/** + * dts file for Hisilicon D03 Development Board + * + * Copyright (C) 2016 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +/dts-v1/; + +#include "hip06.dtsi" + +/ { + model = "Hisilicon Hip06 D03 Development Board"; + compatible = "hisilicon,hip06-d03"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x40000000>; + }; + + chosen { }; +}; + +ð0 { + status = "ok"; +}; + +ð1 { + status = "ok"; +}; + +ð2 { + status = "ok"; +}; + +ð3 { + status = "ok"; +}; + +&sas1 { + status = "ok"; +}; + +&usb_ohci { + status = "ok"; +}; + +&usb_ehci { + status = "ok"; +}; diff --git a/Platforms/Hisilicon/DeviceTree/hip06.dtsi b/Platforms/Hisilicon/DeviceTree/hip06.dtsi new file mode 100644 index 0000000..a049b64 --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hip06.dtsi @@ -0,0 +1,681 @@ +/** + * dts file for Hisilicon D03 Development Board + * + * Copyright (C) 2016 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +#include + +/ { + compatible = "hisilicon,hip06-d03"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu8>; + }; + core1 { + cpu = <&cpu9>; + }; + core2 { + cpu = <&cpu10>; + }; + core3 { + cpu = <&cpu11>; + }; + }; + cluster3 { + core0 { + cpu = <&cpu12>; + }; + core1 { + cpu = <&cpu13>; + }; + core2 { + cpu = <&cpu14>; + }; + core3 { + cpu = <&cpu15>; + }; + }; + }; + + cpu0: cpu@10000 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10000>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu1: cpu@10001 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10001>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu2: cpu@10002 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10002>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu3: cpu@10003 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10003>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu4: cpu@10100 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10100>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu5: cpu@10101 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10101>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu6: cpu@10102 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10102>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu7: cpu@10103 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10103>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu8: cpu@10200 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10200>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + }; + + cpu9: cpu@10201 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10201>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + }; + + cpu10: cpu@10202 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10202>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + }; + + cpu11: cpu@10203 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10203>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + }; + + cpu12: cpu@10300 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10300>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cpu13: cpu@10301 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10301>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cpu14: cpu@10302 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10302>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cpu15: cpu@10303 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x10303>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + }; + + cluster2_l2: l2-cache2 { + compatible = "cache"; + }; + + cluster3_l2: l2-cache3 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@4d000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x30000>; + reg = <0x0 0x4d000000 0 0x10000>, /* GICD */ + <0x0 0x4d100000 0 0x300000>, /* GICR */ + <0x0 0xfe000000 0 0x10000>, /* GICC */ + <0x0 0xfe010000 0 0x10000>, /* GICH */ + <0x0 0xfe020000 0 0x10000>; /* GICV */ + interrupts = ; + + its_dsa: interrupt-controller@c6000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xc6000000 0x0 0x40000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a57-pmu"; + interrupts = ; + }; + + mbigen_pcie@a0080000 { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0xa0080000 0x0 0x10000>; + + mbigen_usb: intc_usb { + msi-parent = <&its_dsa 0x40080>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <2>; + }; + + mbigen_sas1: intc_sas1 { + msi-parent = <&its_dsa 0x40000>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <128>; + }; + + mbigen_sas2: intc_sas2 { + msi-parent = <&its_dsa 0x40040>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <128>; + }; + }; + + mbigen_dsa@c0080000 { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0xc0080000 0x0 0x10000>; + + mbigen_dsaf0: intc_dsaf0 { + msi-parent = <&its_dsa 0x40800>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <409>; + }; + + mbigen_sas0: intc-sas0 { + msi-parent = <&its_dsa 0x40900>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <128>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + refclk: refclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + + usb_ohci: ohci@a7030000 { + compatible = "generic-ohci"; + reg = <0x0 0xa7030000 0x0 0x10000>; + interrupt-parent = <&mbigen_usb>; + interrupts = <640 4>; + dma-coherent; + status = "disabled"; + }; + + usb_ehci: ehci@a7020000 { + compatible = "generic-ehci"; + reg = <0x0 0xa7020000 0x0 0x10000>; + interrupt-parent = <&mbigen_usb>; + interrupts = <641 4>; + dma-coherent; + status = "disabled"; + }; + + peri_c_subctrl: sub_ctrl_c@60000000 { + compatible = "hisilicon,peri-subctrl","syscon"; + reg = <0 0x60000000 0x0 0x10000>; + }; + + dsa_subctrl: dsa_subctrl@c0000000 { + compatible = "hisilicon,dsa-subctrl", "syscon"; + reg = <0x0 0xc0000000 0x0 0x10000>; + }; + + pcie_subctl: pcie_subctl@a0000000 { + compatible = "hisilicon,pcie-sas-subctrl", "syscon"; + reg = <0x0 0xa0000000 0x0 0x10000>; + }; + + serdes_ctrl: sds_ctrl@c2200000 { + compatible = "syscon"; + reg = <0 0xc2200000 0x0 0x80000>; + }; + + mdio@603c0000 { + compatible = "hisilicon,hns-mdio"; + reg = <0x0 0x603c0000 0x0 0x1000>; + subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; + + dsaf0: dsa@c7000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "hisilicon,hns-dsaf-v2"; + mode = "6port-16rss"; + reg = <0x0 0xc5000000 0x0 0x890000 + 0x0 0xc7000000 0x0 0x600000>; + reg-names = "ppe-base", "dsaf-base"; + interrupt-parent = <&mbigen_dsaf0>; + subctrl-syscon = <&dsa_subctrl>; + reset-field-offset = <0>; + interrupts = + <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, + <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, + <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, + <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, + <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, + <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, + <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, + <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, + <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, + <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, + <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, + <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, + <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, + <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, + <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, + <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, + <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, + <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, + <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, + <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, + <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, + <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, + <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, + <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, + <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, + <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, + <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, + <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, + <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, + <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, + <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, + <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, + <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, + <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, + <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, + <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, + <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, + <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, + <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, + <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, + <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, + <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, + <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, + <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, + <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, + <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, + <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, + <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, + <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, + <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, + <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, + <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, + <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, + <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, + <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, + <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, + <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, + <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, + <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, + <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, + <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, + <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, + <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, + <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, + <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, + <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, + <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, + <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, + <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, + <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, + <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, + <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, + <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, + <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, + <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, + <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, + <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, + <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, + <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, + <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, + <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, + <1340 1>, <1341 1>, <1342 1>, <1343 1>; + + desc-num = <0x400>; + buf-size = <0x1000>; + dma-coherent; + + port@0 { + reg = <0>; + serdes-syscon = <&serdes_ctrl>; + port-rst-offset = <0>; + port-mode-offset = <0>; + media-type = "fiber"; + }; + + port@1 { + reg = <1>; + serdes-syscon= <&serdes_ctrl>; + port-rst-offset = <1>; + port-mode-offset = <1>; + media-type = "fiber"; + }; + + port@4 { + reg = <4>; + phy-handle = <&phy0>; + serdes-syscon= <&serdes_ctrl>; + port-rst-offset = <4>; + port-mode-offset = <2>; + media-type = "copper"; + }; + + port@5 { + reg = <5>; + phy-handle = <&phy1>; + serdes-syscon= <&serdes_ctrl>; + port-rst-offset = <5>; + port-mode-offset = <3>; + media-type = "copper"; + }; + }; + + eth0: ethernet-4{ + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <4>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth1: ethernet-5{ + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <5>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth2: ethernet-0{ + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <0>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth3: ethernet-1{ + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <1>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + sas0: sas@c3000000 { + compatible = "hisilicon,hip06-sas-v2"; + reg = <0 0xc3000000 0 0x10000>; + sas-addr = [50 01 88 20 16 00 00 00]; + hisilicon,sas-syscon = <&dsa_subctrl>; + ctrl-reset-reg = <0xa60>; + ctrl-reset-sts-reg = <0x5a30>; + ctrl-clock-ena-reg = <0x338>; + clocks = <&refclk 0>; + queue-count = <16>; + phy-count = <8>; + dma-coherent; + interrupt-parent = <&mbigen_sas0>; + interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, + <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, + <75 4>,<76 4>,<77 4>,<78 4>,<79 4>, + <80 4>,<81 4>,<82 4>,<83 4>,<84 4>, + <85 4>,<86 4>,<87 4>,<88 4>,<89 4>, + <90 4>,<91 4>,<92 4>,<93 4>,<94 4>, + <95 4>,<96 4>,<97 4>,<98 4>,<99 4>, + <100 4>,<101 4>,<102 4>,<103 4>,<104 4>, + <105 4>,<106 4>,<107 4>,<108 4>,<109 4>, + <110 4>,<111 4>,<112 4>,<113 4>,<114 4>, + <115 4>,<116 4>,<117 4>,<118 4>,<119 4>, + <120 4>,<121 4>,<122 4>,<123 4>,<124 4>, + <125 4>,<126 4>,<127 4>,<128 4>,<129 4>, + <130 4>,<131 4>,<132 4>,<133 4>,<134 4>, + <135 4>,<136 4>,<137 4>,<138 4>,<139 4>, + <140 4>,<141 4>,<142 4>,<143 4>,<144 4>, + <145 4>,<146 4>,<147 4>,<148 4>,<149 4>, + <150 4>,<151 4>,<152 4>,<153 4>,<154 4>, + <155 4>,<156 4>,<157 4>,<158 4>,<159 4>, + <160 4>,<601 1>,<602 1>,<603 1>,<604 1>, + <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, + <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, + <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, + <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, + <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, + <630 1>,<631 1>,<632 1>; + status = "disabled"; + }; + + sas1: sas@a2000000 { + compatible = "hisilicon,hip06-sas-v2"; + reg = <0 0xa2000000 0 0x10000>; + sas-addr = [50 01 88 20 16 00 00 00]; + hisilicon,sas-syscon = <&pcie_subctl>; + hip06-sas-v2-quirk-amt; + ctrl-reset-reg = <0xa18>; + ctrl-reset-sts-reg = <0x5a0c>; + ctrl-clock-ena-reg = <0x318>; + clocks = <&refclk 0>; + queue-count = <16>; + phy-count = <8>; + dma-coherent; + interrupt-parent = <&mbigen_sas1>; + interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, + <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, + <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, + <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, + <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, + <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, + <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, + <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, + <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, + <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, + <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, + <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, + <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, + <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, + <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, + <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, + <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, + <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, + <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, + <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, + <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, + <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, + <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, + <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, + <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, + <605 1>,<606 1>,<607 1>; + status = "disabled"; + }; + + sas2: sas@a3000000 { + compatible = "hisilicon,hip06-sas-v2"; + reg = <0 0xa3000000 0 0x10000>; + sas-addr = [50 01 88 20 16 00 00 00]; + hisilicon,sas-syscon = <&pcie_subctl>; + ctrl-reset-reg = <0xae0>; + ctrl-reset-sts-reg = <0x5a70>; + ctrl-clock-ena-reg = <0x3a8>; + clocks = <&refclk 0>; + queue-count = <16>; + phy-count = <9>; + dma-coherent; + interrupt-parent = <&mbigen_sas2>; + interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, + <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, + <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, + <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, + <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, + <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, + <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, + <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, + <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, + <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, + <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, + <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, + <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, + <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, + <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, + <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, + <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, + <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, + <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, + <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, + <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, + <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, + <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, + <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, + <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, + <637 1>,<638 1>,<639 1>; + status = "disabled"; + }; + }; + +}; diff --git a/Platforms/Hisilicon/DeviceTree/hip07-d05.dtb b/Platforms/Hisilicon/DeviceTree/hip07-d05.dtb new file mode 100644 index 0000000..04ad022 Binary files /dev/null and b/Platforms/Hisilicon/DeviceTree/hip07-d05.dtb differ diff --git a/Platforms/Hisilicon/DeviceTree/hip07-d05.dts b/Platforms/Hisilicon/DeviceTree/hip07-d05.dts new file mode 100644 index 0000000..fe7c16c --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hip07-d05.dts @@ -0,0 +1,90 @@ +/** + * dts file for Hisilicon D05 Development Board + * + * Copyright (C) 2016 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +/dts-v1/; + +#include "hip07.dtsi" + +/ { + model = "Hisilicon Hip07 D05 Development Board"; + compatible = "hisilicon,hip07-d05"; + + /* the mem node will be updated by UEFI. */ + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x40000000>; + numa-node-id = <0>; + }; + + distance-map { + compatible = "numa-distance-map-v1"; + distance-matrix = <0 0 10>, + <0 1 15>, + <0 2 20>, + <0 3 25>, + <1 0 15>, + <1 1 10>, + <1 2 25>, + <1 3 30>, + <2 0 20>, + <2 1 25>, + <2 2 10>, + <2 3 15>, + <3 0 25>, + <3 1 30>, + <3 2 15>, + <3 3 10>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "ok"; +}; + +&usb_ohci { + status = "ok"; +}; + +&usb_ehci { + status = "ok"; +}; + +ð0 { + status = "ok"; +}; + +ð1 { + status = "ok"; +}; + +ð2 { + status = "ok"; +}; + +ð3 { + status = "ok"; +}; + +&sas1 { + status = "ok"; +}; + +&p0_pcie2_a { + status = "ok"; +}; diff --git a/Platforms/Hisilicon/DeviceTree/hip07.dtsi b/Platforms/Hisilicon/DeviceTree/hip07.dtsi new file mode 100644 index 0000000..2c01a21 --- /dev/null +++ b/Platforms/Hisilicon/DeviceTree/hip07.dtsi @@ -0,0 +1,1560 @@ +/** + * dts file for Hisilicon D05 Development Board + * + * Copyright (C) 2016 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + * + */ + +#include + +/ { + compatible = "hisilicon,hip07-d05"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu8>; + }; + core1 { + cpu = <&cpu9>; + }; + core2 { + cpu = <&cpu10>; + }; + core3 { + cpu = <&cpu11>; + }; + }; + + cluster3 { + core0 { + cpu = <&cpu12>; + }; + core1 { + cpu = <&cpu13>; + }; + core2 { + cpu = <&cpu14>; + }; + core3 { + cpu = <&cpu15>; + }; + }; + + cluster4 { + core0 { + cpu = <&cpu16>; + }; + core1 { + cpu = <&cpu17>; + }; + core2 { + cpu = <&cpu18>; + }; + core3 { + cpu = <&cpu19>; + }; + }; + + cluster5 { + core0 { + cpu = <&cpu20>; + }; + core1 { + cpu = <&cpu21>; + }; + core2 { + cpu = <&cpu22>; + }; + core3 { + cpu = <&cpu23>; + }; + }; + + cluster6 { + core0 { + cpu = <&cpu24>; + }; + core1 { + cpu = <&cpu25>; + }; + core2 { + cpu = <&cpu26>; + }; + core3 { + cpu = <&cpu27>; + }; + }; + + cluster7 { + core0 { + cpu = <&cpu28>; + }; + core1 { + cpu = <&cpu29>; + }; + core2 { + cpu = <&cpu30>; + }; + core3 { + cpu = <&cpu31>; + }; + }; + + cluster8 { + core0 { + cpu = <&cpu32>; + }; + core1 { + cpu = <&cpu33>; + }; + core2 { + cpu = <&cpu34>; + }; + core3 { + cpu = <&cpu35>; + }; + }; + + cluster9 { + core0 { + cpu = <&cpu36>; + }; + core1 { + cpu = <&cpu37>; + }; + core2 { + cpu = <&cpu38>; + }; + core3 { + cpu = <&cpu39>; + }; + }; + + cluster10 { + core0 { + cpu = <&cpu40>; + }; + core1 { + cpu = <&cpu41>; + }; + core2 { + cpu = <&cpu42>; + }; + core3 { + cpu = <&cpu43>; + }; + }; + + cluster11 { + core0 { + cpu = <&cpu44>; + }; + core1 { + cpu = <&cpu45>; + }; + core2 { + cpu = <&cpu46>; + }; + core3 { + cpu = <&cpu47>; + }; + }; + + cluster12 { + core0 { + cpu = <&cpu48>; + }; + core1 { + cpu = <&cpu49>; + }; + core2 { + cpu = <&cpu50>; + }; + core3 { + cpu = <&cpu51>; + }; + }; + + cluster13 { + core0 { + cpu = <&cpu52>; + }; + core1 { + cpu = <&cpu53>; + }; + core2 { + cpu = <&cpu54>; + }; + core3 { + cpu = <&cpu55>; + }; + }; + + cluster14 { + core0 { + cpu = <&cpu56>; + }; + core1 { + cpu = <&cpu57>; + }; + core2 { + cpu = <&cpu58>; + }; + core3 { + cpu = <&cpu59>; + }; + }; + + cluster15 { + core0 { + cpu = <&cpu60>; + }; + core1 { + cpu = <&cpu61>; + }; + core2 { + cpu = <&cpu62>; + }; + core3 { + cpu = <&cpu63>; + }; + }; + }; + + cpu0: cpu@10000 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10000>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + numa-node-id = <0>; + }; + + cpu1: cpu@10001 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10001>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + numa-node-id = <0>; + }; + + cpu2: cpu@10002 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10002>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + numa-node-id = <0>; + }; + + cpu3: cpu@10003 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10003>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + numa-node-id = <0>; + }; + + cpu4: cpu@10100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10100>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + numa-node-id = <0>; + }; + + cpu5: cpu@10101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10101>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + numa-node-id = <0>; + }; + + cpu6: cpu@10102 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10102>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + numa-node-id = <0>; + }; + + cpu7: cpu@10103 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10103>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + numa-node-id = <0>; + }; + + cpu8: cpu@10200 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10200>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + numa-node-id = <0>; + }; + + cpu9: cpu@10201 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10201>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + numa-node-id = <0>; + }; + + cpu10: cpu@10202 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10202>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + numa-node-id = <0>; + }; + + cpu11: cpu@10203 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10203>; + enable-method = "psci"; + next-level-cache = <&cluster2_l2>; + numa-node-id = <0>; + }; + + cpu12: cpu@10300 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10300>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + numa-node-id = <0>; + }; + + cpu13: cpu@10301 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10301>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + numa-node-id = <0>; + }; + + cpu14: cpu@10302 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10302>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + numa-node-id = <0>; + }; + + cpu15: cpu@10303 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x10303>; + enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + numa-node-id = <0>; + }; + + cpu16: cpu@30000 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30000>; + enable-method = "psci"; + next-level-cache = <&cluster4_l2>; + numa-node-id = <1>; + }; + + cpu17: cpu@30001 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30001>; + enable-method = "psci"; + next-level-cache = <&cluster4_l2>; + numa-node-id = <1>; + }; + + cpu18: cpu@30002 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30002>; + enable-method = "psci"; + next-level-cache = <&cluster4_l2>; + numa-node-id = <1>; + }; + + cpu19: cpu@30003 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30003>; + enable-method = "psci"; + next-level-cache = <&cluster4_l2>; + numa-node-id = <1>; + }; + + cpu20: cpu@30100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30100>; + enable-method = "psci"; + next-level-cache = <&cluster5_l2>; + numa-node-id = <1>; + }; + + cpu21: cpu@30101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30101>; + enable-method = "psci"; + next-level-cache = <&cluster5_l2>; + numa-node-id = <1>; + }; + + cpu22: cpu@30102 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30102>; + enable-method = "psci"; + next-level-cache = <&cluster5_l2>; + numa-node-id = <1>; + }; + + cpu23: cpu@30103 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30103>; + enable-method = "psci"; + next-level-cache = <&cluster5_l2>; + numa-node-id = <1>; + }; + + cpu24: cpu@30200 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30200>; + enable-method = "psci"; + next-level-cache = <&cluster6_l2>; + numa-node-id = <1>; + }; + + cpu25: cpu@30201 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30201>; + enable-method = "psci"; + next-level-cache = <&cluster6_l2>; + numa-node-id = <1>; + }; + + cpu26: cpu@30202 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30202>; + enable-method = "psci"; + next-level-cache = <&cluster6_l2>; + numa-node-id = <1>; + }; + + cpu27: cpu@30203 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30203>; + enable-method = "psci"; + next-level-cache = <&cluster6_l2>; + numa-node-id = <1>; + }; + + cpu28: cpu@30300 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30300>; + enable-method = "psci"; + next-level-cache = <&cluster7_l2>; + numa-node-id = <1>; + }; + + cpu29: cpu@30301 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30301>; + enable-method = "psci"; + next-level-cache = <&cluster7_l2>; + numa-node-id = <1>; + }; + + cpu30: cpu@30302 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30302>; + enable-method = "psci"; + next-level-cache = <&cluster7_l2>; + numa-node-id = <1>; + }; + + cpu31: cpu@30303 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x30303>; + enable-method = "psci"; + next-level-cache = <&cluster7_l2>; + numa-node-id = <1>; + }; + + cpu32: cpu@50000 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50000>; + enable-method = "psci"; + next-level-cache = <&cluster8_l2>; + numa-node-id = <2>; + }; + + cpu33: cpu@50001 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50001>; + enable-method = "psci"; + next-level-cache = <&cluster8_l2>; + numa-node-id = <2>; + }; + + cpu34: cpu@50002 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50002>; + enable-method = "psci"; + next-level-cache = <&cluster8_l2>; + numa-node-id = <2>; + }; + + cpu35: cpu@50003 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50003>; + enable-method = "psci"; + next-level-cache = <&cluster8_l2>; + numa-node-id = <2>; + }; + + cpu36: cpu@50100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50100>; + enable-method = "psci"; + next-level-cache = <&cluster9_l2>; + numa-node-id = <2>; + }; + + cpu37: cpu@50101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50101>; + enable-method = "psci"; + next-level-cache = <&cluster9_l2>; + numa-node-id = <2>; + }; + + cpu38: cpu@50102 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50102>; + enable-method = "psci"; + next-level-cache = <&cluster9_l2>; + numa-node-id = <2>; + }; + + cpu39: cpu@50103 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50103>; + enable-method = "psci"; + next-level-cache = <&cluster9_l2>; + numa-node-id = <2>; + }; + + cpu40: cpu@50200 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50200>; + enable-method = "psci"; + next-level-cache = <&cluster10_l2>; + numa-node-id = <2>; + }; + + cpu41: cpu@50201 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50201>; + enable-method = "psci"; + next-level-cache = <&cluster10_l2>; + numa-node-id = <2>; + }; + + cpu42: cpu@50202 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50202>; + enable-method = "psci"; + next-level-cache = <&cluster10_l2>; + numa-node-id = <2>; + }; + + cpu43: cpu@50203 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50203>; + enable-method = "psci"; + next-level-cache = <&cluster10_l2>; + numa-node-id = <2>; + }; + + cpu44: cpu@50300 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50300>; + enable-method = "psci"; + next-level-cache = <&cluster11_l2>; + numa-node-id = <2>; + }; + + cpu45: cpu@50301 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50301>; + enable-method = "psci"; + next-level-cache = <&cluster11_l2>; + numa-node-id = <2>; + }; + + cpu46: cpu@50302 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50302>; + enable-method = "psci"; + next-level-cache = <&cluster11_l2>; + numa-node-id = <2>; + }; + + cpu47: cpu@50303 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x50303>; + enable-method = "psci"; + next-level-cache = <&cluster11_l2>; + numa-node-id = <2>; + }; + + cpu48: cpu@70000 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70000>; + enable-method = "psci"; + next-level-cache = <&cluster12_l2>; + numa-node-id = <3>; + }; + + cpu49: cpu@70001 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70001>; + enable-method = "psci"; + next-level-cache = <&cluster12_l2>; + numa-node-id = <3>; + }; + + cpu50: cpu@70002 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70002>; + enable-method = "psci"; + next-level-cache = <&cluster12_l2>; + numa-node-id = <3>; + }; + + cpu51: cpu@70003 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70003>; + enable-method = "psci"; + next-level-cache = <&cluster12_l2>; + numa-node-id = <3>; + }; + + cpu52: cpu@70100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70100>; + enable-method = "psci"; + next-level-cache = <&cluster13_l2>; + numa-node-id = <3>; + }; + + cpu53: cpu@70101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70101>; + enable-method = "psci"; + next-level-cache = <&cluster13_l2>; + numa-node-id = <3>; + }; + + cpu54: cpu@70102 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70102>; + enable-method = "psci"; + next-level-cache = <&cluster13_l2>; + numa-node-id = <3>; + }; + + cpu55: cpu@70103 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70103>; + enable-method = "psci"; + next-level-cache = <&cluster13_l2>; + numa-node-id = <3>; + }; + + cpu56: cpu@70200 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70200>; + enable-method = "psci"; + next-level-cache = <&cluster14_l2>; + numa-node-id = <3>; + }; + + cpu57: cpu@70201 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70201>; + enable-method = "psci"; + next-level-cache = <&cluster14_l2>; + numa-node-id = <3>; + }; + + cpu58: cpu@70202 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70202>; + enable-method = "psci"; + next-level-cache = <&cluster14_l2>; + numa-node-id = <3>; + }; + + cpu59: cpu@70203 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70203>; + enable-method = "psci"; + next-level-cache = <&cluster14_l2>; + numa-node-id = <3>; + }; + + cpu60: cpu@70300 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70300>; + enable-method = "psci"; + next-level-cache = <&cluster15_l2>; + numa-node-id = <3>; + }; + + cpu61: cpu@70301 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70301>; + enable-method = "psci"; + next-level-cache = <&cluster15_l2>; + numa-node-id = <3>; + }; + + cpu62: cpu@70302 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70302>; + enable-method = "psci"; + next-level-cache = <&cluster15_l2>; + numa-node-id = <3>; + }; + + cpu63: cpu@70303 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x70303>; + enable-method = "psci"; + next-level-cache = <&cluster15_l2>; + numa-node-id = <3>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + }; + + cluster2_l2: l2-cache2 { + compatible = "cache"; + }; + + cluster3_l2: l2-cache3 { + compatible = "cache"; + }; + + cluster4_l2: l2-cache4 { + compatible = "cache"; + }; + + cluster5_l2: l2-cache5 { + compatible = "cache"; + }; + + cluster6_l2: l2-cache6 { + compatible = "cache"; + }; + + cluster7_l2: l2-cache7 { + compatible = "cache"; + }; + + cluster8_l2: l2-cache8 { + compatible = "cache"; + }; + + cluster9_l2: l2-cache9 { + compatible = "cache"; + }; + + cluster10_l2: l2-cache10 { + compatible = "cache"; + }; + + cluster11_l2: l2-cache11 { + compatible = "cache"; + }; + + cluster12_l2: l2-cache12 { + compatible = "cache"; + }; + + cluster13_l2: l2-cache13 { + compatible = "cache"; + }; + + cluster14_l2: l2-cache14 { + compatible = "cache"; + }; + + cluster15_l2: l2-cache15 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@4d000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <4>; + redistributor-stride = <0x0 0x40000>; + reg = <0x0 0x4d000000 0x0 0x10000>, /* GICD */ + <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */ + <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */ + <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */ + <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */ + <0x0 0xfe000000 0x0 0x10000>, /* GICC */ + <0x0 0xfe010000 0x0 0x10000>, /* GICH */ + <0x0 0xfe020000 0x0 0x10000>; /* GICV */ + interrupts = ; + + p0_its_peri_a: interrupt-controller@4c000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x4c000000 0x0 0x40000>; + }; + + p0_its_peri_b: interrupt-controller@6c000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x6c000000 0x0 0x40000>; + }; + + p0_its_dsa_a: interrupt-controller@c6000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xc6000000 0x0 0x40000>; + }; + + p0_its_dsa_b: interrupt-controller@8,c6000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x8 0xc6000000 0x0 0x40000>; + }; + + p1_its_peri_a: interrupt-controller@400,4c000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x400 0x4c000000 0x0 0x40000>; + }; + + p1_its_peri_b: interrupt-controller@400,6c000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x400 0x6c000000 0x0 0x40000>; + }; + + p1_its_dsa_a: interrupt-controller@400,c6000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x400 0xc6000000 0x0 0x40000>; + }; + + p1_its_dsa_b: interrupt-controller@408,c6000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x408 0xc6000000 0x0 0x40000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + p0_mbigen_peri_b: interrupt-controller@60080000 { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0x60080000 0x0 0x10000>; + + mbigen_uart: uart_intc { + msi-parent = <&p0_its_peri_b 0x120c7>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <1>; + }; + }; + + p0_mbigen_pcie_a: interrupt-controller@a0080000 { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0xa0080000 0x0 0x10000>; + + mbigen_pcie2_a: intc_pcie2_a { + msi-parent = <&p0_its_dsa_a 0x40087>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <10>; + }; + + mbigen_sas1: intc_sas1 { + msi-parent = <&p0_its_dsa_a 0x40000>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <128>; + }; + + mbigen_sas2: intc_sas2 { + msi-parent = <&p0_its_dsa_a 0x40040>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <128>; + }; + + mbigen_smmu_pcie: intc_smmu_pcie { + msi-parent = <&p0_its_dsa_a 0x40b0c>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <3>; + }; + + mbigen_usb: intc_usb { + msi-parent = <&p0_its_dsa_a 0x40080>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <2>; + }; + }; + + p0_mbigen_dsa_a: interrupt-controller@c0080000 { + compatible = "hisilicon,mbigen-v2"; + reg = <0x0 0xc0080000 0x0 0x10000>; + + mbigen_dsaf0: intc_dsaf0 { + msi-parent = <&p0_its_dsa_a 0x40800>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <409>; + }; + + mbigen_dsa_roce: intc-roce { + msi-parent = <&p0_its_dsa_a 0x40B1E>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <34>; + }; + + mbigen_sas0: intc-sas0 { + msi-parent = <&p0_its_dsa_a 0x40900>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <128>; + }; + + mbigen_smmu_dsa: intc_smmu_dsa { + msi-parent = <&p0_its_dsa_a 0x40b20>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <3>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: uart@602b0000 { + compatible = "arm,sbsa-uart"; + reg = <0x0 0x602b0000 0x0 0x1000>; + interrupt-parent = <&mbigen_uart>; + interrupts = <807 4>; + current-speed = <115200>; + reg-io-width = <4>; + status = "disabled"; + }; + + usb_ohci: ohci@a7030000 { + compatible = "generic-ohci"; + reg = <0x0 0xa7030000 0x0 0x10000>; + interrupt-parent = <&mbigen_usb>; + interrupts = <640 4>; + dma-coherent; + status = "disabled"; + }; + + usb_ehci: ehci@a7020000 { + compatible = "generic-ehci"; + reg = <0x0 0xa7020000 0x0 0x10000>; + interrupt-parent = <&mbigen_usb>; + interrupts = <641 4>; + dma-coherent; + status = "disabled"; + }; + + peri_c_subctrl: sub_ctrl_c@60000000 { + compatible = "hisilicon,peri-subctrl","syscon"; + reg = <0 0x60000000 0x0 0x10000>; + }; + + dsa_subctrl: dsa_subctrl@c0000000 { + compatible = "hisilicon,dsa-subctrl", "syscon"; + reg = <0x0 0xc0000000 0x0 0x10000>; + }; + + pcie_subctl: pcie_subctl@a0000000 { + compatible = "hisilicon,pcie-sas-subctrl", "syscon"; + reg = <0x0 0xa0000000 0x0 0x10000>; + }; + + serdes_ctrl: sds_ctrl@c2200000 { + compatible = "syscon"; + reg = <0 0xc2200000 0x0 0x80000>; + }; + + mdio@603c0000 { + compatible = "hisilicon,hns-mdio"; + reg = <0x0 0x603c0000 0x0 0x1000>; + subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 + 0x531c 0x5a1c>; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; + + dsaf0: dsa@c7000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "hisilicon,hns-dsaf-v2"; + mode = "6port-16rss"; + reg = <0x0 0xc5000000 0x0 0x890000 + 0x0 0xc7000000 0x0 0x600000>; + reg-names = "ppe-base", "dsaf-base"; + interrupt-parent = <&mbigen_dsaf0>; + subctrl-syscon = <&dsa_subctrl>; + reset-field-offset = <0>; + interrupts = + <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, + <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, + <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, + <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, + <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, + <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, + <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, + <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, + <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, + <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, + <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, + <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, + <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, + <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, + <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, + <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, + <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, + <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, + <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, + <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, + <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, + <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, + <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, + <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, + <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, + <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, + <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, + <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, + <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, + <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, + <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, + <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, + <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, + <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, + <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, + <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, + <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, + <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, + <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, + <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, + <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, + <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, + <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, + <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, + <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, + <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, + <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, + <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, + <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, + <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, + <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, + <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, + <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, + <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, + <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, + <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, + <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, + <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, + <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, + <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, + <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, + <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, + <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, + <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, + <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, + <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, + <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, + <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, + <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, + <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, + <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, + <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, + <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, + <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, + <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, + <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, + <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, + <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, + <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, + <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, + <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, + <1340 1>, <1341 1>, <1342 1>, <1343 1>; + + desc-num = <0x400>; + buf-size = <0x1000>; + dma-coherent; + + port@0 { + reg = <0>; + serdes-syscon = <&serdes_ctrl>; + port-rst-offset = <0>; + port-mode-offset = <0>; + mc-mac-mask = [ff f0 00 00 00 00]; + media-type = "fiber"; + }; + + port@1 { + reg = <1>; + serdes-syscon= <&serdes_ctrl>; + port-rst-offset = <1>; + port-mode-offset = <1>; + mc-mac-mask = [ff f0 00 00 00 00]; + media-type = "fiber"; + }; + + port@4 { + reg = <4>; + phy-handle = <&phy0>; + serdes-syscon= <&serdes_ctrl>; + port-rst-offset = <4>; + port-mode-offset = <2>; + mc-mac-mask = [ff f0 00 00 00 00]; + media-type = "copper"; + }; + + port@5 { + reg = <5>; + phy-handle = <&phy1>; + serdes-syscon= <&serdes_ctrl>; + port-rst-offset = <5>; + port-mode-offset = <3>; + mc-mac-mask = [ff f0 00 00 00 00]; + media-type = "copper"; + }; + }; + + eth0: ethernet@4{ + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <4>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth1: ethernet@5{ + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <5>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth2: ethernet@0{ + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <0>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth3: ethernet@1{ + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <1>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + infiniband@c4000000 { + compatible = "hisilicon,hns-roce-v1"; + reg = <0x0 0xc4000000 0x0 0x100000>; + dma-coherent; + eth-handle = <ð2 ð3 0 0 ð0 ð1>; + dsaf-handle = <&dsaf0>; + node-guid = [00 9A CD 00 00 01 02 03]; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mbigen_dsa_roce>; + interrupts = <722 1>, + <723 1>, + <724 1>, + <725 1>, + <726 1>, + <727 1>, + <728 1>, + <729 1>, + <730 1>, + <731 1>, + <732 1>, + <733 1>, + <734 1>, + <735 1>, + <736 1>, + <737 1>, + <738 1>, + <739 1>, + <740 1>, + <741 1>, + <742 1>, + <743 1>, + <744 1>, + <745 1>, + <746 1>, + <747 1>, + <748 1>, + <749 1>, + <750 1>, + <751 1>, + <752 1>, + <753 1>, + <785 1>, + <754 4>; + + interrupt-names = "hns-roce-comp-0", + "hns-roce-comp-1", + "hns-roce-comp-2", + "hns-roce-comp-3", + "hns-roce-comp-4", + "hns-roce-comp-5", + "hns-roce-comp-6", + "hns-roce-comp-7", + "hns-roce-comp-8", + "hns-roce-comp-9", + "hns-roce-comp-10", + "hns-roce-comp-11", + "hns-roce-comp-12", + "hns-roce-comp-13", + "hns-roce-comp-14", + "hns-roce-comp-15", + "hns-roce-comp-16", + "hns-roce-comp-17", + "hns-roce-comp-18", + "hns-roce-comp-19", + "hns-roce-comp-20", + "hns-roce-comp-21", + "hns-roce-comp-22", + "hns-roce-comp-23", + "hns-roce-comp-24", + "hns-roce-comp-25", + "hns-roce-comp-26", + "hns-roce-comp-27", + "hns-roce-comp-28", + "hns-roce-comp-29", + "hns-roce-comp-30", + "hns-roce-comp-31", + "hns-roce-async", + "hns-roce-common"; + }; + + sas0: sas@c3000000 { + compatible = "hisilicon,hip07-sas-v2"; + reg = <0 0xc3000000 0 0x10000>; + sas-addr = [50 01 88 20 16 00 00 00]; + hisilicon,sas-syscon = <&dsa_subctrl>; + ctrl-reset-reg = <0xa60>; + ctrl-reset-sts-reg = <0x5a30>; + ctrl-clock-ena-reg = <0x338>; + queue-count = <16>; + phy-count = <8>; + dma-coherent; + interrupt-parent = <&mbigen_sas0>; + interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, + <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, + <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, + <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, + <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, + <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, + <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, + <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, + <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, + <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, + <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, + <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, + <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, + <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, + <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, + <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, + <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, + <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, + <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, + <159 4>,<601 1>,<602 1>,<603 1>,<604 1>, + <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, + <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, + <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, + <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, + <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, + <630 1>,<631 1>,<632 1>; + status = "disabled"; + }; + + sas1: sas@a2000000 { + compatible = "hisilicon,hip07-sas-v2"; + reg = <0 0xa2000000 0 0x10000>; + sas-addr = [50 01 88 20 16 00 00 00]; + hisilicon,sas-syscon = <&pcie_subctl>; + hip06-sas-v2-quirk-amt; + ctrl-reset-reg = <0xa18>; + ctrl-reset-sts-reg = <0x5a0c>; + ctrl-clock-ena-reg = <0x318>; + queue-count = <16>; + phy-count = <8>; + dma-coherent; + interrupt-parent = <&mbigen_sas1>; + interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, + <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, + <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, + <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, + <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, + <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, + <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, + <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, + <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, + <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, + <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, + <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, + <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, + <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, + <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, + <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, + <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, + <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, + <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, + <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, + <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, + <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, + <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, + <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, + <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, + <605 1>,<606 1>,<607 1>; + status = "disabled"; + }; + + sas2: sas@a3000000 { + compatible = "hisilicon,hip07-sas-v2"; + reg = <0 0xa3000000 0 0x10000>; + sas-addr = [50 01 88 20 16 00 00 00]; + hisilicon,sas-syscon = <&pcie_subctl>; + ctrl-reset-reg = <0xae0>; + ctrl-reset-sts-reg = <0x5a70>; + ctrl-clock-ena-reg = <0x3a8>; + queue-count = <16>; + phy-count = <9>; + dma-coherent; + interrupt-parent = <&mbigen_sas2>; + interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, + <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, + <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, + <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, + <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, + <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, + <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, + <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, + <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, + <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, + <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, + <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, + <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, + <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, + <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, + <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, + <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, + <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, + <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, + <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, + <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, + <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, + <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, + <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, + <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, + <637 1>,<638 1>,<639 1>; + status = "disabled"; + }; + + p0_pcie2_a: pcie@a00a0000 { + compatible = "hisilicon,hip07-pcie-ecam"; + reg = <0 0xaf800000 0 0x800000>, + <0 0xa00a0000 0 0x10000>; + bus-range = <0xf8 0xff>; + msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>; + msi-map-mask = <0xffff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000 + 0x01000000 0 0 0 0xaf7f0000 0 0x10000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4 + 0x0 0 0 2 &mbigen_pcie2_a 671 4 + 0x0 0 0 3 &mbigen_pcie2_a 671 4 + 0x0 0 0 4 &mbigen_pcie2_a 671 4>; + status = "disabled"; + }; + }; +}; -- cgit v1.2.3 From 1fc29c7e0cd921d3f06f1e5c86f10c4ec768ba1f Mon Sep 17 00:00:00 2001 From: Riku Voipio Date: Wed, 24 Jan 2018 14:14:38 +0200 Subject: Hisilicon: Embed device trees to firmware Firmware provided device tree is preferred for Generic Linux distributions (Debian, Ubuntu, Fedora, Suse). The main motivation is to have an identical rootfs than can work on many different devices. The alternative is to Bundle Kernel + dtb, or have board-specific grub files. Both would mean board-specific rootfs. This change uses DtPlatformDtbLoaderLib, either backported lib in edk2 is required or rebasing edk2 to newer upstream version. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Riku Voipio --- Platforms/Hisilicon/HiKey/HiKey.dsc | 4 ++++ Platforms/Hisilicon/HiKey/HiKey.fdf | 7 +++++++ Platforms/Hisilicon/HiKey960/HiKey960.dsc | 5 +++++ Platforms/Hisilicon/HiKey960/HiKey960.fdf | 6 ++++++ 4 files changed, 22 insertions(+) diff --git a/Platforms/Hisilicon/HiKey/HiKey.dsc b/Platforms/Hisilicon/HiKey/HiKey.dsc index 28bc47d..7078bae 100644 --- a/Platforms/Hisilicon/HiKey/HiKey.dsc +++ b/Platforms/Hisilicon/HiKey/HiKey.dsc @@ -158,6 +158,7 @@ NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf [LibraryClasses.common.DXE_RUNTIME_DRIVER] CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf @@ -496,6 +497,9 @@ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf FatPkg/EnhancedFatDxe/Fat.inf + # DTB + EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + # # Bds # diff --git a/Platforms/Hisilicon/HiKey/HiKey.fdf b/Platforms/Hisilicon/HiKey/HiKey.fdf index 91f6f3e..56d6913 100644 --- a/Platforms/Hisilicon/HiKey/HiKey.fdf +++ b/Platforms/Hisilicon/HiKey/HiKey.fdf @@ -209,6 +209,13 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf INF MdeModulePkg/Application/UiApp/UiApp.inf + # add Device Tree to the Firmware Volume + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW = OpenPlatformPkg/Platforms/Hisilicon/DeviceTree/hi6220-hikey.dtb + } + + [FV.FVMAIN_COMPACT] FvAlignment = 8 ERASE_POLARITY = 1 diff --git a/Platforms/Hisilicon/HiKey960/HiKey960.dsc b/Platforms/Hisilicon/HiKey960/HiKey960.dsc index bf02a29..16eacc0 100644 --- a/Platforms/Hisilicon/HiKey960/HiKey960.dsc +++ b/Platforms/Hisilicon/HiKey960/HiKey960.dsc @@ -159,6 +159,7 @@ NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf [LibraryClasses.common.DXE_RUNTIME_DRIVER] HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf @@ -486,6 +487,10 @@ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # DTB + EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf # # USB Peripheral Support diff --git a/Platforms/Hisilicon/HiKey960/HiKey960.fdf b/Platforms/Hisilicon/HiKey960/HiKey960.fdf index ec94e60..c36b1be 100644 --- a/Platforms/Hisilicon/HiKey960/HiKey960.fdf +++ b/Platforms/Hisilicon/HiKey960/HiKey960.fdf @@ -215,6 +215,12 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf INF MdeModulePkg/Application/UiApp/UiApp.inf + # add Device Tree to the Firmware Volume + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW = OpenPlatformPkg/Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dtb + } + [FV.FVMAIN_COMPACT] FvAlignment = 8 -- cgit v1.2.3 From d3f28dccc00bc84f81bccb8f7f254d0ba16343cb Mon Sep 17 00:00:00 2001 From: Riku Voipio Date: Fri, 2 Feb 2018 15:55:00 +0200 Subject: remove unneeded device trees Remove unneeded device trees and add UFS bindings for hikey960 --- Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dtb | Bin 32130 -> 32444 bytes Platforms/Hisilicon/DeviceTree/hi3660.dtsi | 20 + .../Hisilicon/DeviceTree/hi3798cv200-poplar.dtb | Bin 8882 -> 0 bytes .../Hisilicon/DeviceTree/hi3798cv200-poplar.dts | 168 --- Platforms/Hisilicon/DeviceTree/hi3798cv200.dtsi | 423 ------ Platforms/Hisilicon/DeviceTree/hip05-d02.dtb | Bin 7035 -> 0 bytes Platforms/Hisilicon/DeviceTree/hip05-d02.dts | 88 -- Platforms/Hisilicon/DeviceTree/hip05.dtsi | 369 ----- Platforms/Hisilicon/DeviceTree/hip06-d03.dtb | Bin 15226 -> 0 bytes Platforms/Hisilicon/DeviceTree/hip06-d03.dts | 54 - Platforms/Hisilicon/DeviceTree/hip06.dtsi | 681 --------- Platforms/Hisilicon/DeviceTree/hip07-d05.dtb | Bin 29415 -> 0 bytes Platforms/Hisilicon/DeviceTree/hip07-d05.dts | 90 -- Platforms/Hisilicon/DeviceTree/hip07.dtsi | 1560 -------------------- 14 files changed, 20 insertions(+), 3433 deletions(-) delete mode 100644 Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dtb delete mode 100644 Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dts delete mode 100644 Platforms/Hisilicon/DeviceTree/hi3798cv200.dtsi delete mode 100644 Platforms/Hisilicon/DeviceTree/hip05-d02.dtb delete mode 100644 Platforms/Hisilicon/DeviceTree/hip05-d02.dts delete mode 100644 Platforms/Hisilicon/DeviceTree/hip05.dtsi delete mode 100644 Platforms/Hisilicon/DeviceTree/hip06-d03.dtb delete mode 100644 Platforms/Hisilicon/DeviceTree/hip06-d03.dts delete mode 100644 Platforms/Hisilicon/DeviceTree/hip06.dtsi delete mode 100644 Platforms/Hisilicon/DeviceTree/hip07-d05.dtb delete mode 100644 Platforms/Hisilicon/DeviceTree/hip07-d05.dts delete mode 100644 Platforms/Hisilicon/DeviceTree/hip07.dtsi diff --git a/Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dtb b/Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dtb index 5ccaf0b..8f6cdde 100644 Binary files a/Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dtb and b/Platforms/Hisilicon/DeviceTree/hi3660-hikey960.dtb differ diff --git a/Platforms/Hisilicon/DeviceTree/hi3660.dtsi b/Platforms/Hisilicon/DeviceTree/hi3660.dtsi index 63d4f9d..c694a34 100644 --- a/Platforms/Hisilicon/DeviceTree/hi3660.dtsi +++ b/Platforms/Hisilicon/DeviceTree/hi3660.dtsi @@ -916,6 +916,26 @@ reset-gpios = <&gpio11 1 0 >; }; + /* UFS */ + ufs: ufs@ff3b0000 { + compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; + /* 0: HCI standard */ + /* 1: UFS SYS CTRL */ + reg = <0x0 0xff3b0000 0x0 0x1000>, + <0x0 0xff3b1000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, + <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; + clock-names = "ref_clk", "phy_clk"; + freq-table-hz = <0 0>, <0 0>; + /* offset: 0x84; bit: 12 */ + /* offset: 0x84; bit: 7 */ + resets = <&crg_rst 0x84 12>, + <&crg_rst 0x84 7>; + reset-names = "rst", "assert"; + }; + /* SD */ dwmmc1: dwmmc1@ff37f000 { #address-cells = <1>; diff --git a/Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dtb b/Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dtb deleted file mode 100644 index 50a07b6..0000000 Binary files a/Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dtb and /dev/null differ diff --git a/Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dts b/Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dts deleted file mode 100644 index 4d5d644..0000000 --- a/Platforms/Hisilicon/DeviceTree/hi3798cv200-poplar.dts +++ /dev/null @@ -1,168 +0,0 @@ -/* - * DTS File for HiSilicon Poplar Development Board - * - * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - * - * Released under the GPLv2 only. - * SPDX-License-Identifier: GPL-2.0 - */ - -/dts-v1/; - -#include -#include "hi3798cv200.dtsi" - -/ { - model = "HiSilicon Poplar Development Board"; - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; - - aliases { - serial0 = &uart0; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - - user-led0 { - label = "USER-LED0"; - gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - user-led1 { - label = "USER-LED1"; - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - user-led2 { - label = "USER-LED2"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - default-state = "off"; - }; - - user-led3 { - label = "USER-LED3"; - gpios = <&gpio10 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - }; -}; - -&gmac1 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <ð_phy1>; - phy-mode = "rgmii"; - hisilicon,phy-reset-delays-us = <10000 10000 30000>; - - eth_phy1: phy@3 { - reg = <3>; - }; -}; - -&gpio1 { - status = "okay"; - gpio-line-names = "GPIO-E", "", - "", "", - "", "GPIO-F", - "", "GPIO-J"; -}; - -&gpio2 { - status = "okay"; - gpio-line-names = "GPIO-H", "GPIO-I", - "GPIO-L", "GPIO-G", - "GPIO-K", "", - "", ""; -}; - -&gpio3 { - status = "okay"; - gpio-line-names = "", "", - "", "", - "GPIO-C", "", - "", "GPIO-B"; -}; - -&gpio4 { - status = "okay"; - gpio-line-names = "", "", - "", "", - "", "GPIO-D", - "", ""; -}; - -&gpio5 { - status = "okay"; - gpio-line-names = "", "USER-LED-1", - "USER-LED-2", "", - "", "GPIO-A", - "", ""; -}; - -&gpio6 { - status = "okay"; - gpio-line-names = "", "", - "", "USER-LED-0", - "", "", - "", ""; -}; - -&gpio10 { - status = "okay"; - gpio-line-names = "", "", - "", "", - "", "", - "USER-LED-3", ""; -}; - -&i2c0 { - status = "okay"; - label = "LS-I2C0"; -}; - -&i2c2 { - status = "okay"; - label = "LS-I2C1"; -}; - -&ir { - status = "okay"; -}; - -&sd0 { - bus-width = <4>; - cap-sd-highspeed; - status = "okay"; -}; - -&spi0 { - status = "okay"; - label = "LS-SPI0"; -}; - -&uart0 { - status = "okay"; -}; - -&uart2 { - status = "okay"; - label = "LS-UART0"; -}; -/* No optional LS-UART1 on Low Speed Expansion Connector. */ diff --git a/Platforms/Hisilicon/DeviceTree/hi3798cv200.dtsi b/Platforms/Hisilicon/DeviceTree/hi3798cv200.dtsi deleted file mode 100644 index 962bd79..0000000 --- a/Platforms/Hisilicon/DeviceTree/hi3798cv200.dtsi +++ /dev/null @@ -1,423 +0,0 @@ -/* - * DTS File for HiSilicon Hi3798cv200 SoC. - * - * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - * - * Released under the GPLv2 only. - * SPDX-License-Identifier: GPL-2.0 - */ - -#include -#include -#include - -/ { - compatible = "hisilicon,hi3798cv200"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x100>; /* GICC */ - #address-cells = <0>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc: soc@f0000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xf0000000 0x10000000>; - - crg: clock-reset-controller@8a22000 { - compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; - reg = <0x8a22000 0x1000>; - #clock-cells = <1>; - #reset-cells = <2>; - - gmacphyrst: reset-controller { - compatible = "ti,syscon-reset"; - #reset-cells = <1>; - ti,reset-bits = - <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | - DEASSERT_SET|STATUS_NONE)>, - <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | - DEASSERT_SET|STATUS_NONE)>; - }; - }; - - sysctrl: system-controller@8000000 { - compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; - reg = <0x8000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <2>; - }; - - uart0: serial@8b00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x8b00000 0x1000>; - interrupts = ; - clocks = <&sysctrl HISTB_UART0_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart2: serial@8b02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x8b02000 0x1000>; - interrupts = ; - clocks = <&crg HISTB_UART2_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@8b10000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b10000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C0_CLK>; - status = "disabled"; - }; - - i2c1: i2c@8b11000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b11000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C1_CLK>; - status = "disabled"; - }; - - i2c2: i2c@8b12000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b12000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C2_CLK>; - status = "disabled"; - }; - - i2c3: i2c@8b13000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b13000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C3_CLK>; - status = "disabled"; - }; - - i2c4: i2c@8b14000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b14000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C4_CLK>; - status = "disabled"; - }; - - spi0: spi@8b1a000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x8b1a000 0x1000>; - interrupts = ; - num-cs = <1>; - cs-gpios = <&gpio7 1 0>; - clocks = <&crg HISTB_SPI0_CLK>; - clock-names = "apb_pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sd0: mmc@9820000 { - compatible = "snps,dw-mshc"; - reg = <0x9820000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_SDIO0_CIU_CLK>, - <&crg HISTB_SDIO0_BIU_CLK>; - clock-names = "ciu", "biu"; - resets = <&crg 0x9c 4>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@9830000 { - compatible = "snps,dw-mshc"; - reg = <0x9830000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_MMC_CIU_CLK>, - <&crg HISTB_MMC_BIU_CLK>; - clock-names = "ciu", "biu"; - }; - - gpio0: gpio@8b20000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b20000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio1: gpio@8b21000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b21000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio2: gpio@8b22000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b22000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio3: gpio@8b23000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b23000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio4: gpio@8b24000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b24000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio5: gpio@8004000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8004000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio6: gpio@8b26000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b26000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio7: gpio@8b27000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b27000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio8: gpio@8b28000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b28000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio9: gpio@8b29000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b29000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio10: gpio@8b2a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b2a000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio11: gpio@8b2b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b2b000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio12: gpio@8b2c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b2c000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gmac0: ethernet@9840000 { - compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; - reg = <0x9840000 0x1000>, - <0x984300c 0x4>; - interrupts = ; - clocks = <&crg HISTB_ETH0_MAC_CLK>, - <&crg HISTB_ETH0_MACIF_CLK>; - clock-names = "mac_core", "mac_ifc"; - resets = <&crg 0xcc 8>, - <&crg 0xcc 10>, - <&gmacphyrst 0>; - reset-names = "mac_core", "mac_ifc", "phy"; - status = "disabled"; - }; - - gmac1: ethernet@9841000 { - compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; - reg = <0x9841000 0x1000>, - <0x9843010 0x4>; - interrupts = ; - clocks = <&crg HISTB_ETH1_MAC_CLK>, - <&crg HISTB_ETH1_MACIF_CLK>; - clock-names = "mac_core", "mac_ifc"; - resets = <&crg 0xcc 9>, - <&crg 0xcc 11>, - <&gmacphyrst 1>; - reset-names = "mac_core", "mac_ifc", "phy"; - status = "disabled"; - }; - - ir: ir@8001000 { - compatible = "hisilicon,hix5hd2-ir"; - reg = <0x8001000 0x1000>; - interrupts = ; - clocks = <&sysctrl HISTB_IR_CLK>; - status = "disabled"; - }; - }; -}; diff --git a/Platforms/Hisilicon/DeviceTree/hip05-d02.dtb b/Platforms/Hisilicon/DeviceTree/hip05-d02.dtb deleted file mode 100644 index d90d915..0000000 Binary files a/Platforms/Hisilicon/DeviceTree/hip05-d02.dtb and /dev/null differ diff --git a/Platforms/Hisilicon/DeviceTree/hip05-d02.dts b/Platforms/Hisilicon/DeviceTree/hip05-d02.dts deleted file mode 100644 index 3bbd017..0000000 --- a/Platforms/Hisilicon/DeviceTree/hip05-d02.dts +++ /dev/null @@ -1,88 +0,0 @@ -/** - * dts file for Hisilicon D02 Development Board - * - * Copyright (C) 2014,2015 Hisilicon Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - * - */ - -/dts-v1/; - -#include -#include "hip05.dtsi" - -/ { - model = "Hisilicon Hip05 D02 Development Board"; - compatible = "hisilicon,hip05-d02"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x80000000>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - pwrbutton { - label = "Power Button"; - gpios = <&porta 8 GPIO_ACTIVE_LOW>; - linux,code = <116>; - debounce-interval = <0>; - }; - }; -}; - -&uart0 { - status = "ok"; -}; - -&peri_gpio0 { - status = "ok"; -}; - -&lbc { - status = "ok"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x90000000 0x08000000>, - <1 0 0x0 0x98000000 0x08000000>; - - nor-flash@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "numonyx,js28f00a", "cfi-flash"; - reg = <0 0x0 0x08000000>; - bank-width = <2>; - /* The three parts may not used */ - partition@0 { - label = "BIOS"; - reg = <0x0 0x300000>; - }; - partition@300000 { - label = "Linux"; - reg = <0x300000 0xa00000>; - }; - partition@1000000 { - label = "Rootfs"; - reg = <0x01000000 0x02000000>; - }; - }; - - cpld@1,0 { - compatible = "hisilicon,hip05-cpld"; - reg = <1 0x0 0x100>; - }; -}; diff --git a/Platforms/Hisilicon/DeviceTree/hip05.dtsi b/Platforms/Hisilicon/DeviceTree/hip05.dtsi deleted file mode 100644 index 4b472a3..0000000 --- a/Platforms/Hisilicon/DeviceTree/hip05.dtsi +++ /dev/null @@ -1,369 +0,0 @@ -/** - * dts file for Hisilicon D02 Development Board - * - * Copyright (C) 2014,2015 Hisilicon Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - * - */ - -#include - -/ { - compatible = "hisilicon,hip05-d02"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - cluster2 { - core0 { - cpu = <&cpu8>; - }; - core1 { - cpu = <&cpu9>; - }; - core2 { - cpu = <&cpu10>; - }; - core3 { - cpu = <&cpu11>; - }; - }; - cluster3 { - core0 { - cpu = <&cpu12>; - }; - core1 { - cpu = <&cpu13>; - }; - core2 { - cpu = <&cpu14>; - }; - core3 { - cpu = <&cpu15>; - }; - }; - }; - - cpu0: cpu@20000 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20000>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu1: cpu@20001 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20001>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu2: cpu@20002 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20002>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu3: cpu@20003 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20003>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu4: cpu@20100 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20100>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu5: cpu@20101 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20101>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu6: cpu@20102 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20102>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu7: cpu@20103 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20103>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu8: cpu@20200 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20200>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu9: cpu@20201 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20201>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu10: cpu@20202 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20202>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu11: cpu@20203 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20203>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu12: cpu@20300 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20300>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu13: cpu@20301 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20301>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu14: cpu@20302 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20302>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu15: cpu@20303 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x20303>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@8d000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x30000>; - reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ - <0x0 0x8d100000 0 0x300000>, /* GICR */ - <0x0 0xfe000000 0 0x10000>, /* GICC */ - <0x0 0xfe010000 0 0x10000>, /* GICH */ - <0x0 0xfe020000 0 0x10000>; /* GICV */ - interrupts = ; - - its_peri: interrupt-controller@8c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x8c000000 0x0 0x40000>; - }; - - its_m3: interrupt-controller@a3000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xa3000000 0x0 0x40000>; - }; - - its_pcie: interrupt-controller@b7000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xb7000000 0x0 0x40000>; - }; - - its_dsa: interrupt-controller@c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xc6000000 0x0 0x40000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a57-pmu"; - interrupts = ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - refclk200mhz: refclk200mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - uart0: uart@80300000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x80300000 0x0 0x10000>; - interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: uart@80310000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x80310000 0x0 0x10000>; - interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - lbc: localbus@80380000 { - compatible = "hisilicon,hisi-localbus", "simple-bus"; - reg = <0x0 0x80380000 0x0 0x10000>; - status = "disabled"; - }; - - peri_gpio0: gpio@802e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x802e0000 0x0 0x10000>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - peri_gpio1: gpio@802f0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x802f0000 0x0 0x10000>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - }; -}; diff --git a/Platforms/Hisilicon/DeviceTree/hip06-d03.dtb b/Platforms/Hisilicon/DeviceTree/hip06-d03.dtb deleted file mode 100644 index ea3018e..0000000 Binary files a/Platforms/Hisilicon/DeviceTree/hip06-d03.dtb and /dev/null differ diff --git a/Platforms/Hisilicon/DeviceTree/hip06-d03.dts b/Platforms/Hisilicon/DeviceTree/hip06-d03.dts deleted file mode 100644 index 9af6330..0000000 --- a/Platforms/Hisilicon/DeviceTree/hip06-d03.dts +++ /dev/null @@ -1,54 +0,0 @@ -/** - * dts file for Hisilicon D03 Development Board - * - * Copyright (C) 2016 Hisilicon Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - * - */ - -/dts-v1/; - -#include "hip06.dtsi" - -/ { - model = "Hisilicon Hip06 D03 Development Board"; - compatible = "hisilicon,hip06-d03"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x40000000>; - }; - - chosen { }; -}; - -ð0 { - status = "ok"; -}; - -ð1 { - status = "ok"; -}; - -ð2 { - status = "ok"; -}; - -ð3 { - status = "ok"; -}; - -&sas1 { - status = "ok"; -}; - -&usb_ohci { - status = "ok"; -}; - -&usb_ehci { - status = "ok"; -}; diff --git a/Platforms/Hisilicon/DeviceTree/hip06.dtsi b/Platforms/Hisilicon/DeviceTree/hip06.dtsi deleted file mode 100644 index a049b64..0000000 --- a/Platforms/Hisilicon/DeviceTree/hip06.dtsi +++ /dev/null @@ -1,681 +0,0 @@ -/** - * dts file for Hisilicon D03 Development Board - * - * Copyright (C) 2016 Hisilicon Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - * - */ - -#include - -/ { - compatible = "hisilicon,hip06-d03"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - cluster2 { - core0 { - cpu = <&cpu8>; - }; - core1 { - cpu = <&cpu9>; - }; - core2 { - cpu = <&cpu10>; - }; - core3 { - cpu = <&cpu11>; - }; - }; - cluster3 { - core0 { - cpu = <&cpu12>; - }; - core1 { - cpu = <&cpu13>; - }; - core2 { - cpu = <&cpu14>; - }; - core3 { - cpu = <&cpu15>; - }; - }; - }; - - cpu0: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10000>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu1: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10001>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu2: cpu@10002 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10002>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu3: cpu@10003 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10003>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu4: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10100>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu5: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10101>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu6: cpu@10102 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10102>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu7: cpu@10103 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10103>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu8: cpu@10200 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10200>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu9: cpu@10201 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10201>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu10: cpu@10202 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10202>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu11: cpu@10203 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10203>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu12: cpu@10300 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10300>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu13: cpu@10301 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10301>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu14: cpu@10302 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10302>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu15: cpu@10303 { - device_type = "cpu"; - compatible = "arm,cortex-a57", "arm,armv8"; - reg = <0x10303>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@4d000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x30000>; - reg = <0x0 0x4d000000 0 0x10000>, /* GICD */ - <0x0 0x4d100000 0 0x300000>, /* GICR */ - <0x0 0xfe000000 0 0x10000>, /* GICC */ - <0x0 0xfe010000 0 0x10000>, /* GICH */ - <0x0 0xfe020000 0 0x10000>; /* GICV */ - interrupts = ; - - its_dsa: interrupt-controller@c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xc6000000 0x0 0x40000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a57-pmu"; - interrupts = ; - }; - - mbigen_pcie@a0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xa0080000 0x0 0x10000>; - - mbigen_usb: intc_usb { - msi-parent = <&its_dsa 0x40080>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <2>; - }; - - mbigen_sas1: intc_sas1 { - msi-parent = <&its_dsa 0x40000>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_sas2: intc_sas2 { - msi-parent = <&its_dsa 0x40040>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - }; - - mbigen_dsa@c0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xc0080000 0x0 0x10000>; - - mbigen_dsaf0: intc_dsaf0 { - msi-parent = <&its_dsa 0x40800>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <409>; - }; - - mbigen_sas0: intc-sas0 { - msi-parent = <&its_dsa 0x40900>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - refclk: refclk { - compatible = "fixed-clock"; - clock-frequency = <50000000>; - #clock-cells = <0>; - }; - - usb_ohci: ohci@a7030000 { - compatible = "generic-ohci"; - reg = <0x0 0xa7030000 0x0 0x10000>; - interrupt-parent = <&mbigen_usb>; - interrupts = <640 4>; - dma-coherent; - status = "disabled"; - }; - - usb_ehci: ehci@a7020000 { - compatible = "generic-ehci"; - reg = <0x0 0xa7020000 0x0 0x10000>; - interrupt-parent = <&mbigen_usb>; - interrupts = <641 4>; - dma-coherent; - status = "disabled"; - }; - - peri_c_subctrl: sub_ctrl_c@60000000 { - compatible = "hisilicon,peri-subctrl","syscon"; - reg = <0 0x60000000 0x0 0x10000>; - }; - - dsa_subctrl: dsa_subctrl@c0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0x0 0xc0000000 0x0 0x10000>; - }; - - pcie_subctl: pcie_subctl@a0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0x0 0xa0000000 0x0 0x10000>; - }; - - serdes_ctrl: sds_ctrl@c2200000 { - compatible = "syscon"; - reg = <0 0xc2200000 0x0 0x80000>; - }; - - mdio@603c0000 { - compatible = "hisilicon,hns-mdio"; - reg = <0x0 0x603c0000 0x0 0x1000>; - subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>; - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; - - dsaf0: dsa@c7000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "hisilicon,hns-dsaf-v2"; - mode = "6port-16rss"; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x600000>; - reg-names = "ppe-base", "dsaf-base"; - interrupt-parent = <&mbigen_dsaf0>; - subctrl-syscon = <&dsa_subctrl>; - reset-field-offset = <0>; - interrupts = - <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, - <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, - <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, - <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, - <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, - <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, - <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, - <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, - <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, - <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, - <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, - <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, - <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, - <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, - <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, - <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, - <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, - <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, - <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, - <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, - <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, - <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, - <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, - <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, - <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, - <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, - <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, - <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, - <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, - <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, - <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, - <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, - <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, - <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, - <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, - <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, - <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, - <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, - <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, - <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, - <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, - <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, - <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, - <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, - <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, - <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, - <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, - <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, - <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, - <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, - <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, - <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, - <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, - <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, - <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, - <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, - <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, - <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, - <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, - <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, - <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, - <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, - <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, - <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, - <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, - <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, - <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, - <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, - <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, - <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, - <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, - <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, - <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, - <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, - <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, - <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, - <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, - <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, - <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, - <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, - <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, - <1340 1>, <1341 1>, <1342 1>, <1343 1>; - - desc-num = <0x400>; - buf-size = <0x1000>; - dma-coherent; - - port@0 { - reg = <0>; - serdes-syscon = <&serdes_ctrl>; - port-rst-offset = <0>; - port-mode-offset = <0>; - media-type = "fiber"; - }; - - port@1 { - reg = <1>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <1>; - port-mode-offset = <1>; - media-type = "fiber"; - }; - - port@4 { - reg = <4>; - phy-handle = <&phy0>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <4>; - port-mode-offset = <2>; - media-type = "copper"; - }; - - port@5 { - reg = <5>; - phy-handle = <&phy1>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <5>; - port-mode-offset = <3>; - media-type = "copper"; - }; - }; - - eth0: ethernet-4{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <4>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth1: ethernet-5{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <5>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth2: ethernet-0{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth3: ethernet-1{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <1>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - sas0: sas@c3000000 { - compatible = "hisilicon,hip06-sas-v2"; - reg = <0 0xc3000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&dsa_subctrl>; - ctrl-reset-reg = <0xa60>; - ctrl-reset-sts-reg = <0x5a30>; - ctrl-clock-ena-reg = <0x338>; - clocks = <&refclk 0>; - queue-count = <16>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_sas0>; - interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, - <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, - <75 4>,<76 4>,<77 4>,<78 4>,<79 4>, - <80 4>,<81 4>,<82 4>,<83 4>,<84 4>, - <85 4>,<86 4>,<87 4>,<88 4>,<89 4>, - <90 4>,<91 4>,<92 4>,<93 4>,<94 4>, - <95 4>,<96 4>,<97 4>,<98 4>,<99 4>, - <100 4>,<101 4>,<102 4>,<103 4>,<104 4>, - <105 4>,<106 4>,<107 4>,<108 4>,<109 4>, - <110 4>,<111 4>,<112 4>,<113 4>,<114 4>, - <115 4>,<116 4>,<117 4>,<118 4>,<119 4>, - <120 4>,<121 4>,<122 4>,<123 4>,<124 4>, - <125 4>,<126 4>,<127 4>,<128 4>,<129 4>, - <130 4>,<131 4>,<132 4>,<133 4>,<134 4>, - <135 4>,<136 4>,<137 4>,<138 4>,<139 4>, - <140 4>,<141 4>,<142 4>,<143 4>,<144 4>, - <145 4>,<146 4>,<147 4>,<148 4>,<149 4>, - <150 4>,<151 4>,<152 4>,<153 4>,<154 4>, - <155 4>,<156 4>,<157 4>,<158 4>,<159 4>, - <160 4>,<601 1>,<602 1>,<603 1>,<604 1>, - <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, - <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, - <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, - <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, - <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, - <630 1>,<631 1>,<632 1>; - status = "disabled"; - }; - - sas1: sas@a2000000 { - compatible = "hisilicon,hip06-sas-v2"; - reg = <0 0xa2000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&pcie_subctl>; - hip06-sas-v2-quirk-amt; - ctrl-reset-reg = <0xa18>; - ctrl-reset-sts-reg = <0x5a0c>; - ctrl-clock-ena-reg = <0x318>; - clocks = <&refclk 0>; - queue-count = <16>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_sas1>; - interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, - <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, - <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, - <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, - <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, - <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, - <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, - <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, - <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, - <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, - <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, - <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, - <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, - <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, - <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, - <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, - <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, - <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, - <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, - <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, - <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, - <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, - <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, - <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, - <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, - <605 1>,<606 1>,<607 1>; - status = "disabled"; - }; - - sas2: sas@a3000000 { - compatible = "hisilicon,hip06-sas-v2"; - reg = <0 0xa3000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&pcie_subctl>; - ctrl-reset-reg = <0xae0>; - ctrl-reset-sts-reg = <0x5a70>; - ctrl-clock-ena-reg = <0x3a8>; - clocks = <&refclk 0>; - queue-count = <16>; - phy-count = <9>; - dma-coherent; - interrupt-parent = <&mbigen_sas2>; - interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, - <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, - <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, - <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, - <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, - <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, - <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, - <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, - <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, - <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, - <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, - <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, - <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, - <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, - <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, - <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, - <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, - <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, - <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, - <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, - <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, - <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, - <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, - <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, - <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, - <637 1>,<638 1>,<639 1>; - status = "disabled"; - }; - }; - -}; diff --git a/Platforms/Hisilicon/DeviceTree/hip07-d05.dtb b/Platforms/Hisilicon/DeviceTree/hip07-d05.dtb deleted file mode 100644 index 04ad022..0000000 Binary files a/Platforms/Hisilicon/DeviceTree/hip07-d05.dtb and /dev/null differ diff --git a/Platforms/Hisilicon/DeviceTree/hip07-d05.dts b/Platforms/Hisilicon/DeviceTree/hip07-d05.dts deleted file mode 100644 index fe7c16c..0000000 --- a/Platforms/Hisilicon/DeviceTree/hip07-d05.dts +++ /dev/null @@ -1,90 +0,0 @@ -/** - * dts file for Hisilicon D05 Development Board - * - * Copyright (C) 2016 Hisilicon Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - * - */ - -/dts-v1/; - -#include "hip07.dtsi" - -/ { - model = "Hisilicon Hip07 D05 Development Board"; - compatible = "hisilicon,hip07-d05"; - - /* the mem node will be updated by UEFI. */ - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x40000000>; - numa-node-id = <0>; - }; - - distance-map { - compatible = "numa-distance-map-v1"; - distance-matrix = <0 0 10>, - <0 1 15>, - <0 2 20>, - <0 3 25>, - <1 0 15>, - <1 1 10>, - <1 2 25>, - <1 3 30>, - <2 0 20>, - <2 1 25>, - <2 2 10>, - <2 3 15>, - <3 0 25>, - <3 1 30>, - <3 2 15>, - <3 3 10>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "ok"; -}; - -&usb_ohci { - status = "ok"; -}; - -&usb_ehci { - status = "ok"; -}; - -ð0 { - status = "ok"; -}; - -ð1 { - status = "ok"; -}; - -ð2 { - status = "ok"; -}; - -ð3 { - status = "ok"; -}; - -&sas1 { - status = "ok"; -}; - -&p0_pcie2_a { - status = "ok"; -}; diff --git a/Platforms/Hisilicon/DeviceTree/hip07.dtsi b/Platforms/Hisilicon/DeviceTree/hip07.dtsi deleted file mode 100644 index 2c01a21..0000000 --- a/Platforms/Hisilicon/DeviceTree/hip07.dtsi +++ /dev/null @@ -1,1560 +0,0 @@ -/** - * dts file for Hisilicon D05 Development Board - * - * Copyright (C) 2016 Hisilicon Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - * - */ - -#include - -/ { - compatible = "hisilicon,hip07-d05"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - - cluster2 { - core0 { - cpu = <&cpu8>; - }; - core1 { - cpu = <&cpu9>; - }; - core2 { - cpu = <&cpu10>; - }; - core3 { - cpu = <&cpu11>; - }; - }; - - cluster3 { - core0 { - cpu = <&cpu12>; - }; - core1 { - cpu = <&cpu13>; - }; - core2 { - cpu = <&cpu14>; - }; - core3 { - cpu = <&cpu15>; - }; - }; - - cluster4 { - core0 { - cpu = <&cpu16>; - }; - core1 { - cpu = <&cpu17>; - }; - core2 { - cpu = <&cpu18>; - }; - core3 { - cpu = <&cpu19>; - }; - }; - - cluster5 { - core0 { - cpu = <&cpu20>; - }; - core1 { - cpu = <&cpu21>; - }; - core2 { - cpu = <&cpu22>; - }; - core3 { - cpu = <&cpu23>; - }; - }; - - cluster6 { - core0 { - cpu = <&cpu24>; - }; - core1 { - cpu = <&cpu25>; - }; - core2 { - cpu = <&cpu26>; - }; - core3 { - cpu = <&cpu27>; - }; - }; - - cluster7 { - core0 { - cpu = <&cpu28>; - }; - core1 { - cpu = <&cpu29>; - }; - core2 { - cpu = <&cpu30>; - }; - core3 { - cpu = <&cpu31>; - }; - }; - - cluster8 { - core0 { - cpu = <&cpu32>; - }; - core1 { - cpu = <&cpu33>; - }; - core2 { - cpu = <&cpu34>; - }; - core3 { - cpu = <&cpu35>; - }; - }; - - cluster9 { - core0 { - cpu = <&cpu36>; - }; - core1 { - cpu = <&cpu37>; - }; - core2 { - cpu = <&cpu38>; - }; - core3 { - cpu = <&cpu39>; - }; - }; - - cluster10 { - core0 { - cpu = <&cpu40>; - }; - core1 { - cpu = <&cpu41>; - }; - core2 { - cpu = <&cpu42>; - }; - core3 { - cpu = <&cpu43>; - }; - }; - - cluster11 { - core0 { - cpu = <&cpu44>; - }; - core1 { - cpu = <&cpu45>; - }; - core2 { - cpu = <&cpu46>; - }; - core3 { - cpu = <&cpu47>; - }; - }; - - cluster12 { - core0 { - cpu = <&cpu48>; - }; - core1 { - cpu = <&cpu49>; - }; - core2 { - cpu = <&cpu50>; - }; - core3 { - cpu = <&cpu51>; - }; - }; - - cluster13 { - core0 { - cpu = <&cpu52>; - }; - core1 { - cpu = <&cpu53>; - }; - core2 { - cpu = <&cpu54>; - }; - core3 { - cpu = <&cpu55>; - }; - }; - - cluster14 { - core0 { - cpu = <&cpu56>; - }; - core1 { - cpu = <&cpu57>; - }; - core2 { - cpu = <&cpu58>; - }; - core3 { - cpu = <&cpu59>; - }; - }; - - cluster15 { - core0 { - cpu = <&cpu60>; - }; - core1 { - cpu = <&cpu61>; - }; - core2 { - cpu = <&cpu62>; - }; - core3 { - cpu = <&cpu63>; - }; - }; - }; - - cpu0: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10000>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - numa-node-id = <0>; - }; - - cpu1: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10001>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - numa-node-id = <0>; - }; - - cpu2: cpu@10002 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10002>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - numa-node-id = <0>; - }; - - cpu3: cpu@10003 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10003>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - numa-node-id = <0>; - }; - - cpu4: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10100>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - numa-node-id = <0>; - }; - - cpu5: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10101>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - numa-node-id = <0>; - }; - - cpu6: cpu@10102 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10102>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - numa-node-id = <0>; - }; - - cpu7: cpu@10103 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10103>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - numa-node-id = <0>; - }; - - cpu8: cpu@10200 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10200>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - numa-node-id = <0>; - }; - - cpu9: cpu@10201 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10201>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - numa-node-id = <0>; - }; - - cpu10: cpu@10202 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10202>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - numa-node-id = <0>; - }; - - cpu11: cpu@10203 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10203>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - numa-node-id = <0>; - }; - - cpu12: cpu@10300 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10300>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - numa-node-id = <0>; - }; - - cpu13: cpu@10301 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10301>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - numa-node-id = <0>; - }; - - cpu14: cpu@10302 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10302>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - numa-node-id = <0>; - }; - - cpu15: cpu@10303 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x10303>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - numa-node-id = <0>; - }; - - cpu16: cpu@30000 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30000>; - enable-method = "psci"; - next-level-cache = <&cluster4_l2>; - numa-node-id = <1>; - }; - - cpu17: cpu@30001 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30001>; - enable-method = "psci"; - next-level-cache = <&cluster4_l2>; - numa-node-id = <1>; - }; - - cpu18: cpu@30002 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30002>; - enable-method = "psci"; - next-level-cache = <&cluster4_l2>; - numa-node-id = <1>; - }; - - cpu19: cpu@30003 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30003>; - enable-method = "psci"; - next-level-cache = <&cluster4_l2>; - numa-node-id = <1>; - }; - - cpu20: cpu@30100 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30100>; - enable-method = "psci"; - next-level-cache = <&cluster5_l2>; - numa-node-id = <1>; - }; - - cpu21: cpu@30101 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30101>; - enable-method = "psci"; - next-level-cache = <&cluster5_l2>; - numa-node-id = <1>; - }; - - cpu22: cpu@30102 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30102>; - enable-method = "psci"; - next-level-cache = <&cluster5_l2>; - numa-node-id = <1>; - }; - - cpu23: cpu@30103 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30103>; - enable-method = "psci"; - next-level-cache = <&cluster5_l2>; - numa-node-id = <1>; - }; - - cpu24: cpu@30200 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30200>; - enable-method = "psci"; - next-level-cache = <&cluster6_l2>; - numa-node-id = <1>; - }; - - cpu25: cpu@30201 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30201>; - enable-method = "psci"; - next-level-cache = <&cluster6_l2>; - numa-node-id = <1>; - }; - - cpu26: cpu@30202 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30202>; - enable-method = "psci"; - next-level-cache = <&cluster6_l2>; - numa-node-id = <1>; - }; - - cpu27: cpu@30203 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30203>; - enable-method = "psci"; - next-level-cache = <&cluster6_l2>; - numa-node-id = <1>; - }; - - cpu28: cpu@30300 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30300>; - enable-method = "psci"; - next-level-cache = <&cluster7_l2>; - numa-node-id = <1>; - }; - - cpu29: cpu@30301 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30301>; - enable-method = "psci"; - next-level-cache = <&cluster7_l2>; - numa-node-id = <1>; - }; - - cpu30: cpu@30302 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30302>; - enable-method = "psci"; - next-level-cache = <&cluster7_l2>; - numa-node-id = <1>; - }; - - cpu31: cpu@30303 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x30303>; - enable-method = "psci"; - next-level-cache = <&cluster7_l2>; - numa-node-id = <1>; - }; - - cpu32: cpu@50000 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50000>; - enable-method = "psci"; - next-level-cache = <&cluster8_l2>; - numa-node-id = <2>; - }; - - cpu33: cpu@50001 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50001>; - enable-method = "psci"; - next-level-cache = <&cluster8_l2>; - numa-node-id = <2>; - }; - - cpu34: cpu@50002 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50002>; - enable-method = "psci"; - next-level-cache = <&cluster8_l2>; - numa-node-id = <2>; - }; - - cpu35: cpu@50003 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50003>; - enable-method = "psci"; - next-level-cache = <&cluster8_l2>; - numa-node-id = <2>; - }; - - cpu36: cpu@50100 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50100>; - enable-method = "psci"; - next-level-cache = <&cluster9_l2>; - numa-node-id = <2>; - }; - - cpu37: cpu@50101 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50101>; - enable-method = "psci"; - next-level-cache = <&cluster9_l2>; - numa-node-id = <2>; - }; - - cpu38: cpu@50102 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50102>; - enable-method = "psci"; - next-level-cache = <&cluster9_l2>; - numa-node-id = <2>; - }; - - cpu39: cpu@50103 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50103>; - enable-method = "psci"; - next-level-cache = <&cluster9_l2>; - numa-node-id = <2>; - }; - - cpu40: cpu@50200 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50200>; - enable-method = "psci"; - next-level-cache = <&cluster10_l2>; - numa-node-id = <2>; - }; - - cpu41: cpu@50201 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50201>; - enable-method = "psci"; - next-level-cache = <&cluster10_l2>; - numa-node-id = <2>; - }; - - cpu42: cpu@50202 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50202>; - enable-method = "psci"; - next-level-cache = <&cluster10_l2>; - numa-node-id = <2>; - }; - - cpu43: cpu@50203 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50203>; - enable-method = "psci"; - next-level-cache = <&cluster10_l2>; - numa-node-id = <2>; - }; - - cpu44: cpu@50300 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50300>; - enable-method = "psci"; - next-level-cache = <&cluster11_l2>; - numa-node-id = <2>; - }; - - cpu45: cpu@50301 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50301>; - enable-method = "psci"; - next-level-cache = <&cluster11_l2>; - numa-node-id = <2>; - }; - - cpu46: cpu@50302 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50302>; - enable-method = "psci"; - next-level-cache = <&cluster11_l2>; - numa-node-id = <2>; - }; - - cpu47: cpu@50303 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x50303>; - enable-method = "psci"; - next-level-cache = <&cluster11_l2>; - numa-node-id = <2>; - }; - - cpu48: cpu@70000 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70000>; - enable-method = "psci"; - next-level-cache = <&cluster12_l2>; - numa-node-id = <3>; - }; - - cpu49: cpu@70001 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70001>; - enable-method = "psci"; - next-level-cache = <&cluster12_l2>; - numa-node-id = <3>; - }; - - cpu50: cpu@70002 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70002>; - enable-method = "psci"; - next-level-cache = <&cluster12_l2>; - numa-node-id = <3>; - }; - - cpu51: cpu@70003 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70003>; - enable-method = "psci"; - next-level-cache = <&cluster12_l2>; - numa-node-id = <3>; - }; - - cpu52: cpu@70100 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70100>; - enable-method = "psci"; - next-level-cache = <&cluster13_l2>; - numa-node-id = <3>; - }; - - cpu53: cpu@70101 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70101>; - enable-method = "psci"; - next-level-cache = <&cluster13_l2>; - numa-node-id = <3>; - }; - - cpu54: cpu@70102 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70102>; - enable-method = "psci"; - next-level-cache = <&cluster13_l2>; - numa-node-id = <3>; - }; - - cpu55: cpu@70103 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70103>; - enable-method = "psci"; - next-level-cache = <&cluster13_l2>; - numa-node-id = <3>; - }; - - cpu56: cpu@70200 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70200>; - enable-method = "psci"; - next-level-cache = <&cluster14_l2>; - numa-node-id = <3>; - }; - - cpu57: cpu@70201 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70201>; - enable-method = "psci"; - next-level-cache = <&cluster14_l2>; - numa-node-id = <3>; - }; - - cpu58: cpu@70202 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70202>; - enable-method = "psci"; - next-level-cache = <&cluster14_l2>; - numa-node-id = <3>; - }; - - cpu59: cpu@70203 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70203>; - enable-method = "psci"; - next-level-cache = <&cluster14_l2>; - numa-node-id = <3>; - }; - - cpu60: cpu@70300 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70300>; - enable-method = "psci"; - next-level-cache = <&cluster15_l2>; - numa-node-id = <3>; - }; - - cpu61: cpu@70301 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70301>; - enable-method = "psci"; - next-level-cache = <&cluster15_l2>; - numa-node-id = <3>; - }; - - cpu62: cpu@70302 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70302>; - enable-method = "psci"; - next-level-cache = <&cluster15_l2>; - numa-node-id = <3>; - }; - - cpu63: cpu@70303 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0x70303>; - enable-method = "psci"; - next-level-cache = <&cluster15_l2>; - numa-node-id = <3>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - - cluster4_l2: l2-cache4 { - compatible = "cache"; - }; - - cluster5_l2: l2-cache5 { - compatible = "cache"; - }; - - cluster6_l2: l2-cache6 { - compatible = "cache"; - }; - - cluster7_l2: l2-cache7 { - compatible = "cache"; - }; - - cluster8_l2: l2-cache8 { - compatible = "cache"; - }; - - cluster9_l2: l2-cache9 { - compatible = "cache"; - }; - - cluster10_l2: l2-cache10 { - compatible = "cache"; - }; - - cluster11_l2: l2-cache11 { - compatible = "cache"; - }; - - cluster12_l2: l2-cache12 { - compatible = "cache"; - }; - - cluster13_l2: l2-cache13 { - compatible = "cache"; - }; - - cluster14_l2: l2-cache14 { - compatible = "cache"; - }; - - cluster15_l2: l2-cache15 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@4d000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <4>; - redistributor-stride = <0x0 0x40000>; - reg = <0x0 0x4d000000 0x0 0x10000>, /* GICD */ - <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */ - <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */ - <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */ - <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */ - <0x0 0xfe000000 0x0 0x10000>, /* GICC */ - <0x0 0xfe010000 0x0 0x10000>, /* GICH */ - <0x0 0xfe020000 0x0 0x10000>; /* GICV */ - interrupts = ; - - p0_its_peri_a: interrupt-controller@4c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x4c000000 0x0 0x40000>; - }; - - p0_its_peri_b: interrupt-controller@6c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x6c000000 0x0 0x40000>; - }; - - p0_its_dsa_a: interrupt-controller@c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xc6000000 0x0 0x40000>; - }; - - p0_its_dsa_b: interrupt-controller@8,c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x8 0xc6000000 0x0 0x40000>; - }; - - p1_its_peri_a: interrupt-controller@400,4c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x400 0x4c000000 0x0 0x40000>; - }; - - p1_its_peri_b: interrupt-controller@400,6c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x400 0x6c000000 0x0 0x40000>; - }; - - p1_its_dsa_a: interrupt-controller@400,c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x400 0xc6000000 0x0 0x40000>; - }; - - p1_its_dsa_b: interrupt-controller@408,c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x408 0xc6000000 0x0 0x40000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = ; - }; - - p0_mbigen_peri_b: interrupt-controller@60080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0x60080000 0x0 0x10000>; - - mbigen_uart: uart_intc { - msi-parent = <&p0_its_peri_b 0x120c7>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <1>; - }; - }; - - p0_mbigen_pcie_a: interrupt-controller@a0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xa0080000 0x0 0x10000>; - - mbigen_pcie2_a: intc_pcie2_a { - msi-parent = <&p0_its_dsa_a 0x40087>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <10>; - }; - - mbigen_sas1: intc_sas1 { - msi-parent = <&p0_its_dsa_a 0x40000>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_sas2: intc_sas2 { - msi-parent = <&p0_its_dsa_a 0x40040>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_smmu_pcie: intc_smmu_pcie { - msi-parent = <&p0_its_dsa_a 0x40b0c>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - - mbigen_usb: intc_usb { - msi-parent = <&p0_its_dsa_a 0x40080>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <2>; - }; - }; - - p0_mbigen_dsa_a: interrupt-controller@c0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xc0080000 0x0 0x10000>; - - mbigen_dsaf0: intc_dsaf0 { - msi-parent = <&p0_its_dsa_a 0x40800>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <409>; - }; - - mbigen_dsa_roce: intc-roce { - msi-parent = <&p0_its_dsa_a 0x40B1E>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <34>; - }; - - mbigen_sas0: intc-sas0 { - msi-parent = <&p0_its_dsa_a 0x40900>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_smmu_dsa: intc_smmu_dsa { - msi-parent = <&p0_its_dsa_a 0x40b20>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: uart@602b0000 { - compatible = "arm,sbsa-uart"; - reg = <0x0 0x602b0000 0x0 0x1000>; - interrupt-parent = <&mbigen_uart>; - interrupts = <807 4>; - current-speed = <115200>; - reg-io-width = <4>; - status = "disabled"; - }; - - usb_ohci: ohci@a7030000 { - compatible = "generic-ohci"; - reg = <0x0 0xa7030000 0x0 0x10000>; - interrupt-parent = <&mbigen_usb>; - interrupts = <640 4>; - dma-coherent; - status = "disabled"; - }; - - usb_ehci: ehci@a7020000 { - compatible = "generic-ehci"; - reg = <0x0 0xa7020000 0x0 0x10000>; - interrupt-parent = <&mbigen_usb>; - interrupts = <641 4>; - dma-coherent; - status = "disabled"; - }; - - peri_c_subctrl: sub_ctrl_c@60000000 { - compatible = "hisilicon,peri-subctrl","syscon"; - reg = <0 0x60000000 0x0 0x10000>; - }; - - dsa_subctrl: dsa_subctrl@c0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0x0 0xc0000000 0x0 0x10000>; - }; - - pcie_subctl: pcie_subctl@a0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0x0 0xa0000000 0x0 0x10000>; - }; - - serdes_ctrl: sds_ctrl@c2200000 { - compatible = "syscon"; - reg = <0 0xc2200000 0x0 0x80000>; - }; - - mdio@603c0000 { - compatible = "hisilicon,hns-mdio"; - reg = <0x0 0x603c0000 0x0 0x1000>; - subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 - 0x531c 0x5a1c>; - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; - - dsaf0: dsa@c7000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "hisilicon,hns-dsaf-v2"; - mode = "6port-16rss"; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x600000>; - reg-names = "ppe-base", "dsaf-base"; - interrupt-parent = <&mbigen_dsaf0>; - subctrl-syscon = <&dsa_subctrl>; - reset-field-offset = <0>; - interrupts = - <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, - <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, - <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, - <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, - <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, - <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, - <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, - <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, - <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, - <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, - <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, - <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, - <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, - <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, - <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, - <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, - <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, - <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, - <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, - <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, - <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, - <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, - <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, - <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, - <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, - <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, - <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, - <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, - <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, - <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, - <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, - <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, - <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, - <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, - <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, - <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, - <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, - <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, - <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, - <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, - <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, - <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, - <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, - <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, - <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, - <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, - <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, - <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, - <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, - <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, - <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, - <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, - <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, - <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, - <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, - <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, - <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, - <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, - <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, - <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, - <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, - <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, - <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, - <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, - <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, - <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, - <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, - <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, - <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, - <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, - <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, - <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, - <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, - <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, - <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, - <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, - <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, - <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, - <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, - <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, - <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, - <1340 1>, <1341 1>, <1342 1>, <1343 1>; - - desc-num = <0x400>; - buf-size = <0x1000>; - dma-coherent; - - port@0 { - reg = <0>; - serdes-syscon = <&serdes_ctrl>; - port-rst-offset = <0>; - port-mode-offset = <0>; - mc-mac-mask = [ff f0 00 00 00 00]; - media-type = "fiber"; - }; - - port@1 { - reg = <1>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <1>; - port-mode-offset = <1>; - mc-mac-mask = [ff f0 00 00 00 00]; - media-type = "fiber"; - }; - - port@4 { - reg = <4>; - phy-handle = <&phy0>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <4>; - port-mode-offset = <2>; - mc-mac-mask = [ff f0 00 00 00 00]; - media-type = "copper"; - }; - - port@5 { - reg = <5>; - phy-handle = <&phy1>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <5>; - port-mode-offset = <3>; - mc-mac-mask = [ff f0 00 00 00 00]; - media-type = "copper"; - }; - }; - - eth0: ethernet@4{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <4>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth1: ethernet@5{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <5>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth2: ethernet@0{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth3: ethernet@1{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <1>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - infiniband@c4000000 { - compatible = "hisilicon,hns-roce-v1"; - reg = <0x0 0xc4000000 0x0 0x100000>; - dma-coherent; - eth-handle = <ð2 ð3 0 0 ð0 ð1>; - dsaf-handle = <&dsaf0>; - node-guid = [00 9A CD 00 00 01 02 03]; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mbigen_dsa_roce>; - interrupts = <722 1>, - <723 1>, - <724 1>, - <725 1>, - <726 1>, - <727 1>, - <728 1>, - <729 1>, - <730 1>, - <731 1>, - <732 1>, - <733 1>, - <734 1>, - <735 1>, - <736 1>, - <737 1>, - <738 1>, - <739 1>, - <740 1>, - <741 1>, - <742 1>, - <743 1>, - <744 1>, - <745 1>, - <746 1>, - <747 1>, - <748 1>, - <749 1>, - <750 1>, - <751 1>, - <752 1>, - <753 1>, - <785 1>, - <754 4>; - - interrupt-names = "hns-roce-comp-0", - "hns-roce-comp-1", - "hns-roce-comp-2", - "hns-roce-comp-3", - "hns-roce-comp-4", - "hns-roce-comp-5", - "hns-roce-comp-6", - "hns-roce-comp-7", - "hns-roce-comp-8", - "hns-roce-comp-9", - "hns-roce-comp-10", - "hns-roce-comp-11", - "hns-roce-comp-12", - "hns-roce-comp-13", - "hns-roce-comp-14", - "hns-roce-comp-15", - "hns-roce-comp-16", - "hns-roce-comp-17", - "hns-roce-comp-18", - "hns-roce-comp-19", - "hns-roce-comp-20", - "hns-roce-comp-21", - "hns-roce-comp-22", - "hns-roce-comp-23", - "hns-roce-comp-24", - "hns-roce-comp-25", - "hns-roce-comp-26", - "hns-roce-comp-27", - "hns-roce-comp-28", - "hns-roce-comp-29", - "hns-roce-comp-30", - "hns-roce-comp-31", - "hns-roce-async", - "hns-roce-common"; - }; - - sas0: sas@c3000000 { - compatible = "hisilicon,hip07-sas-v2"; - reg = <0 0xc3000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&dsa_subctrl>; - ctrl-reset-reg = <0xa60>; - ctrl-reset-sts-reg = <0x5a30>; - ctrl-clock-ena-reg = <0x338>; - queue-count = <16>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_sas0>; - interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, - <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, - <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, - <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, - <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, - <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, - <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, - <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, - <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, - <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, - <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, - <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, - <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, - <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, - <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, - <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, - <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, - <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, - <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, - <159 4>,<601 1>,<602 1>,<603 1>,<604 1>, - <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, - <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, - <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, - <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, - <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, - <630 1>,<631 1>,<632 1>; - status = "disabled"; - }; - - sas1: sas@a2000000 { - compatible = "hisilicon,hip07-sas-v2"; - reg = <0 0xa2000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&pcie_subctl>; - hip06-sas-v2-quirk-amt; - ctrl-reset-reg = <0xa18>; - ctrl-reset-sts-reg = <0x5a0c>; - ctrl-clock-ena-reg = <0x318>; - queue-count = <16>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_sas1>; - interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, - <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, - <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, - <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, - <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, - <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, - <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, - <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, - <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, - <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, - <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, - <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, - <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, - <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, - <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, - <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, - <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, - <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, - <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, - <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, - <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, - <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, - <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, - <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, - <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, - <605 1>,<606 1>,<607 1>; - status = "disabled"; - }; - - sas2: sas@a3000000 { - compatible = "hisilicon,hip07-sas-v2"; - reg = <0 0xa3000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&pcie_subctl>; - ctrl-reset-reg = <0xae0>; - ctrl-reset-sts-reg = <0x5a70>; - ctrl-clock-ena-reg = <0x3a8>; - queue-count = <16>; - phy-count = <9>; - dma-coherent; - interrupt-parent = <&mbigen_sas2>; - interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, - <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, - <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, - <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, - <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, - <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, - <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, - <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, - <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, - <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, - <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, - <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, - <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, - <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, - <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, - <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, - <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, - <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, - <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, - <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, - <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, - <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, - <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, - <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, - <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, - <637 1>,<638 1>,<639 1>; - status = "disabled"; - }; - - p0_pcie2_a: pcie@a00a0000 { - compatible = "hisilicon,hip07-pcie-ecam"; - reg = <0 0xaf800000 0 0x800000>, - <0 0xa00a0000 0 0x10000>; - bus-range = <0xf8 0xff>; - msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>; - msi-map-mask = <0xffff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000 - 0x01000000 0 0 0 0xaf7f0000 0 0x10000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4 - 0x0 0 0 2 &mbigen_pcie2_a 671 4 - 0x0 0 0 3 &mbigen_pcie2_a 671 4 - 0x0 0 0 4 &mbigen_pcie2_a 671 4>; - status = "disabled"; - }; - }; -}; -- cgit v1.2.3 From b3cd251603b69648b952aaf50fdf4a08ad55c2f0 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 7 Feb 2018 09:29:40 +0800 Subject: Revert "Platforms/HiKey: disable SD card temporary" This reverts commit 04680f1f01a0863b3578250f8e5833c39c5b6f75. --- Platforms/Hisilicon/HiKey/HiKey.dsc | 2 +- Platforms/Hisilicon/HiKey/HiKey.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Platforms/Hisilicon/HiKey/HiKey.dsc b/Platforms/Hisilicon/HiKey/HiKey.dsc index 7078bae..6abd9c8 100644 --- a/Platforms/Hisilicon/HiKey/HiKey.dsc +++ b/Platforms/Hisilicon/HiKey/HiKey.dsc @@ -428,7 +428,7 @@ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf OpenPlatformPkg/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.inf MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf - #MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf diff --git a/Platforms/Hisilicon/HiKey/HiKey.fdf b/Platforms/Hisilicon/HiKey/HiKey.fdf index 56d6913..634a6a5 100644 --- a/Platforms/Hisilicon/HiKey/HiKey.fdf +++ b/Platforms/Hisilicon/HiKey/HiKey.fdf @@ -132,7 +132,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf INF OpenPlatformPkg/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.inf INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf - #INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf INF OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf -- cgit v1.2.3 From f9b1e032239ca4f7977c44018f7fd7c116377af8 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 7 Feb 2018 11:23:22 +0800 Subject: Platforms/Hisilicon: remove MBR partition from SD boot path Since SD card may be formated as GPT partition. Signed-off-by: Haojian Zhuang --- Platforms/Hisilicon/HiKey/HiKey.dsc | 2 +- Platforms/Hisilicon/HiKey960/HiKey960.dsc | 2 +- .../Library/PlatformBootManagerLib/PlatformBm.c | 16 ---------------- 3 files changed, 2 insertions(+), 18 deletions(-) diff --git a/Platforms/Hisilicon/HiKey/HiKey.dsc b/Platforms/Hisilicon/HiKey/HiKey.dsc index 6abd9c8..79802a3 100644 --- a/Platforms/Hisilicon/HiKey/HiKey.dsc +++ b/Platforms/Hisilicon/HiKey/HiKey.dsc @@ -359,7 +359,7 @@ # Android Loader # gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00D023F70000000000)/eMMC(0x0)/Ctrl(0x0)/HD(6,GPT,5C0F213C-17E1-4149-88C8-8B50FB4EC70E,0x7000,0x20000)" - gEmbeddedTokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)/HD(1,MBR,0x263000B1,0x3F,0x21FC0)" + gEmbeddedTokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)" gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|1 diff --git a/Platforms/Hisilicon/HiKey960/HiKey960.dsc b/Platforms/Hisilicon/HiKey960/HiKey960.dsc index 16eacc0..8b07b1c 100644 --- a/Platforms/Hisilicon/HiKey960/HiKey960.dsc +++ b/Platforms/Hisilicon/HiKey960/HiKey960.dsc @@ -369,7 +369,7 @@ # Android Loader # gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00003BFF0000000000)/UFS(0x0,0x3)/HD(7,GPT,D3340696-9B95-4C64-8DF6-E6D4548FBA41,0x12100,0x4000)" - gEmbeddedTokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00F037FF0000000000)/SD(0x0)/HD(1,MBR,0x263000B1,0x3F,0x21FC0)" + gEmbeddedTokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00F037FF0000000000)/SD(0x0)" gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|1 diff --git a/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c b/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c index b1586a8..5c59846 100644 --- a/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c +++ b/Platforms/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c @@ -341,9 +341,6 @@ PlatformRegisterBootSd ( CHAR16 *BootPathStr; EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *EfiDevicePathFromTextProtocol; EFI_DEVICE_PATH *DevicePath; - EFI_DEVICE_PATH *FileDevicePath; - FILEPATH_DEVICE_PATH *FilePath; - UINTN Size; EFI_BOOT_MANAGER_LOAD_OPTION NewOption; EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; UINTN BootOptionCount; @@ -359,19 +356,6 @@ PlatformRegisterBootSd ( DevicePath = (EFI_DEVICE_PATH *)EfiDevicePathFromTextProtocol->ConvertTextToDevicePath (BootPathStr); ASSERT (DevicePath != NULL); - Size = StrSize (SD_FILE_NAME); - FileDevicePath = AllocatePool (Size + SIZE_OF_FILEPATH_DEVICE_PATH + END_DEVICE_PATH_LENGTH); - if (FileDevicePath != NULL) { - FilePath = (FILEPATH_DEVICE_PATH *) FileDevicePath; - FilePath->Header.Type = MEDIA_DEVICE_PATH; - FilePath->Header.SubType = MEDIA_FILEPATH_DP; - CopyMem (&FilePath->PathName, SD_FILE_NAME, Size); - SetDevicePathNodeLength (&FilePath->Header, Size + SIZE_OF_FILEPATH_DEVICE_PATH); - SetDevicePathEndNode (NextDevicePathNode (&FilePath->Header)); - - DevicePath = AppendDevicePath (DevicePath, FileDevicePath); - FreePool (FileDevicePath); - } Status = EfiBootManagerInitializeLoadOption ( &NewOption, LoadOptionNumberUnassigned, -- cgit v1.2.3 From 39049e00d3cbd2f095ced2fa3928cabeb052ead5 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Thu, 8 Feb 2018 00:29:09 +0800 Subject: Platforms/Hisilicon: fix arrow keys in release build The key is in the receive FIFO in PL011 driver. This driver supports of 1, 16 or 32 chars. Arrow key is presented as 3 chars. For example, DOWN key is "~[B". By default, PcdUartDefaultReceiveFifoDepth is fixed at 1. It means that arrow key is truncated. So it can't be worked well. After updating to 0, the FIFO depth will be set either 16 or 32 chars. The logic is in below. HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \ > PL011_VER_R1P4) \ ? 32 : 16 ; Signed-off-by: Haojian Zhuang --- Platforms/Hisilicon/HiKey/HiKey.dsc | 1 + Platforms/Hisilicon/HiKey960/HiKey960.dsc | 1 + 2 files changed, 2 insertions(+) diff --git a/Platforms/Hisilicon/HiKey/HiKey.dsc b/Platforms/Hisilicon/HiKey/HiKey.dsc index 28bc47d..6a10988 100644 --- a/Platforms/Hisilicon/HiKey/HiKey.dsc +++ b/Platforms/Hisilicon/HiKey/HiKey.dsc @@ -315,6 +315,7 @@ DEFINE SERIAL_BASE = 0xF7113000 # UART3 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE) gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 gArmPlatformTokenSpaceGuid.PL011UartInteger|10 gArmPlatformTokenSpaceGuid.PL011UartFractional|26 diff --git a/Platforms/Hisilicon/HiKey960/HiKey960.dsc b/Platforms/Hisilicon/HiKey960/HiKey960.dsc index bf02a29..3715209 100644 --- a/Platforms/Hisilicon/HiKey960/HiKey960.dsc +++ b/Platforms/Hisilicon/HiKey960/HiKey960.dsc @@ -311,6 +311,7 @@ DEFINE SERIAL_BASE = 0xFFF32000 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE) gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 gArmPlatformTokenSpaceGuid.PL011UartInteger|10 gArmPlatformTokenSpaceGuid.PL011UartFractional|26 -- cgit v1.2.3 From 389915f98330682871811e5df84195effb55a8d3 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 10 Feb 2018 14:52:54 +0800 Subject: Drivers/SdMmc/DwMmcHcDxe: update interface of card detect Update the interface of card detection with controller handle. Since eMMC and SD controllers are handled as two different controllers on HiKey, slot can't be used to distinguish which controller is working now. Signed-off-by: Haojian Zhuang --- Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.c | 4 ++-- Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c | 3 ++- Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.h | 7 ++++--- Include/Protocol/PlatformDwMmc.h | 1 + 4 files changed, 9 insertions(+), 6 deletions(-) diff --git a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.c b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.c index 55e2fa4..f3c9156 100644 --- a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.c +++ b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHcDxe.c @@ -248,7 +248,7 @@ return; for (Slot = 0; Slot < DW_MMC_HC_MAX_SLOT; Slot++) { if ((Private->Slot[Slot].Enable) && (Private->Slot[Slot].SlotType == RemovableSlot)) { - Status = DwMmcHcCardDetect (Private->PciIo, Slot, &MediaPresent); + Status = DwMmcHcCardDetect (Private->PciIo, Private->ControllerHandle, Slot, &MediaPresent); if ((Status == EFI_MEDIA_CHANGED) && !MediaPresent) { DEBUG ((DEBUG_INFO, "DwMmcHcEnumerateDevice: device disconnected at slot %d of pci %p\n", Slot, Private->PciIo)); Private->Slot[Slot].MediaPresent = FALSE; @@ -679,7 +679,7 @@ DwMmcHcDriverBindingStart ( DumpCapabilityReg (Slot, &Private->Capability[Slot]); MediaPresent = FALSE; - Status = DwMmcHcCardDetect (Private->PciIo, Slot, &MediaPresent); + Status = DwMmcHcCardDetect (Private->PciIo, Controller, Slot, &MediaPresent); if (MediaPresent == FALSE) { continue; } diff --git a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c index 533f911..3d03780 100644 --- a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c +++ b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c @@ -524,6 +524,7 @@ DwMmcHcGetMaxCurrent ( EFI_STATUS DwMmcHcCardDetect ( IN EFI_PCI_IO_PROTOCOL *PciIo, + IN EFI_HANDLE Controller, IN UINT8 Slot, OUT BOOLEAN *MediaPresent ) @@ -542,7 +543,7 @@ DwMmcHcCardDetect ( if (EFI_ERROR (Status)) { return Status; } - *MediaPresent = PlatformDwMmc->CardDetect (Slot); + *MediaPresent = PlatformDwMmc->CardDetect (Controller, Slot); return EFI_SUCCESS; } diff --git a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.h b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.h index 228b20f..d9c6211 100644 --- a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.h +++ b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.h @@ -522,9 +522,10 @@ DwMmcHcGetMaxCurrent ( **/ EFI_STATUS DwMmcHcCardDetect ( - IN EFI_PCI_IO_PROTOCOL *PciIo, - IN UINT8 Slot, - OUT BOOLEAN *MediaPresent + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN EFI_HANDLE Controller, + IN UINT8 Slot, + OUT BOOLEAN *MediaPresent ); /** diff --git a/Include/Protocol/PlatformDwMmc.h b/Include/Protocol/PlatformDwMmc.h index fe2259b..bf315c4 100644 --- a/Include/Protocol/PlatformDwMmc.h +++ b/Include/Protocol/PlatformDwMmc.h @@ -65,6 +65,7 @@ EFI_STATUS typedef BOOLEAN (EFIAPI *PLATFORM_DW_MMC_CARD_DETECT) ( + IN EFI_HANDLE Controller, IN UINT8 Slot ); -- cgit v1.2.3 From b195820461509b3d0ab04674a457a928bdc3a07c Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 10 Feb 2018 14:55:20 +0800 Subject: HiKey/HiKeyMmcDxe: fix on detecting SD card Since eMMC and SD controllers are handled as two controllers, slot can't be used to distinguish these two devices. Signed-off-by: Haojian Zhuang --- Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.c b/Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.c index 0f58697..e7d3c6c 100644 --- a/Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.c +++ b/Platforms/Hisilicon/HiKey/HiKeyMmcDxe/HiKeyMmcDxe.c @@ -79,6 +79,7 @@ HiKeyGetCapability ( BOOLEAN EFIAPI HiKeyCardDetect ( + IN EFI_HANDLE Controller, IN UINT8 Slot ) { @@ -86,9 +87,9 @@ HiKeyCardDetect ( EMBEDDED_GPIO *Gpio; UINTN Value; - if (Slot == 0) { + if (DwMmcCapability[0].Controller == Controller) { return TRUE; - } else if (Slot == 1) { + } else if (DwMmcCapability[1].Controller == Controller) { Status = gBS->LocateProtocol (&gEmbeddedGpioProtocolGuid, NULL, (VOID **)&Gpio); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "Failed to get GPIO protocol: %r\n", Status)); @@ -108,9 +109,8 @@ HiKeyCardDetect ( return TRUE; } return FALSE; - } else { - return FALSE; } + return FALSE; } PLATFORM_DW_MMC_PROTOCOL mDwMmcDevice = { -- cgit v1.2.3 From 41d055fa9be56baf111f6c110773f4413c830a98 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 10 Feb 2018 16:11:19 +0800 Subject: HiKey960/Mmc: update the interface of card detection Update the interface of card detection. The parameter of "controller" is added. Signed-off-by: Haojian Zhuang --- Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.c | 1 + 1 file changed, 1 insertion(+) diff --git a/Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.c b/Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.c index 3e52270..4d8c476 100644 --- a/Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.c +++ b/Platforms/Hisilicon/HiKey960/HiKey960MmcDxe/HiKey960MmcDxe.c @@ -67,6 +67,7 @@ HiKey960GetCapability ( BOOLEAN EFIAPI HiKey960CardDetect ( + IN EFI_HANDLE Controller, IN UINT8 Slot ) { -- cgit v1.2.3 From 4bd897453f5937f01f1ecf6ebda76c0a715be9b0 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 10 Feb 2018 16:49:55 +0800 Subject: Platform/HiKey960: add warning message Add warning message for recovery mode. User shouldn't boot kernel in recovery mode. Since BL31 won't be loaded and some devices are not initialized in recovery mode. Signed-off-by: Haojian Zhuang --- Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c | 14 ++++++++++++++ Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf | 1 + Platforms/Hisilicon/HiKey960/Include/Hi3660.h | 2 ++ 3 files changed, 17 insertions(+) diff --git a/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c b/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c index 6ef1c3d..b4e0e1b 100644 --- a/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c +++ b/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -96,6 +97,12 @@ typedef struct { CHAR16 UnicodeSN[SERIAL_NUMBER_SIZE]; } RANDOM_SERIAL_NUMBER; +enum { + BOOT_MODE_RECOVERY = 0, + BOOT_MODE_NORMAL, + BOOT_MODE_MASK = 1, +}; + STATIC UINTN mBoardId; STATIC EMBEDDED_GPIO *mGpio; @@ -348,6 +355,13 @@ OnEndOfDxe ( IN VOID *Context ) { + UINT32 BootMode; + + BootMode = MmioRead32 (SCTRL_BAK_DATA0) & BOOT_MODE_MASK; + if (BootMode == BOOT_MODE_RECOVERY) { + SerialPortWrite ((UINT8 *)"WARNING: CAN NOT BOOT KERNEL IN RECOVERY MODE!\r\n", 48); + SerialPortWrite ((UINT8 *)"Switch to normal boot mode, then reboot to boot kernel.\r\n", 57); + } } EFI_STATUS diff --git a/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf b/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf index df668a8..f9c0c94 100644 --- a/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf +++ b/Platforms/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf @@ -39,6 +39,7 @@ NonDiscoverableDeviceRegistrationLib PcdLib PrintLib + SerialPortLib TimerLib UefiBootServicesTableLib UefiDriverEntryPoint diff --git a/Platforms/Hisilicon/HiKey960/Include/Hi3660.h b/Platforms/Hisilicon/HiKey960/Include/Hi3660.h index 939f7f0..0d810d8 100644 --- a/Platforms/Hisilicon/HiKey960/Include/Hi3660.h +++ b/Platforms/Hisilicon/HiKey960/Include/Hi3660.h @@ -30,6 +30,8 @@ #define SCTRL_SCFPLLCTRL0 (SCTRL_REG_BASE + 0x120) #define SCTRL_SCFPLLCTRL0_FPLL0_EN (1 << 0) +#define SCTRL_BAK_DATA0 (SCTRL_REG_BASE + 0x40C) + #define USB3OTG_BC_REG_BASE 0xFF200000 #define USB3OTG_CTRL0 (USB3OTG_BC_REG_BASE + 0x000) -- cgit v1.2.3 From 88ff655659d2bd16f47dae5e48259ac7f6311a9d Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 12 Feb 2018 09:05:38 +0800 Subject: Drivers/DwMmcHcDxe: optimize the delay Add timeout on the delay. Signed-off-by: Haojian Zhuang --- Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c index 3d03780..5db5f34 100644 --- a/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c +++ b/Drivers/SdMmc/DwMmcHcDxe/DwMmcHci.c @@ -1522,10 +1522,13 @@ DwEmmcExecTrb ( UINT32 IntStatus; UINT32 Argument; UINT32 ErrMask; + UINT32 Timeout; Packet = Trb->Packet; PciIo = Trb->Private->PciIo; + ArmDataSynchronizationBarrier (); + ArmInstructionSynchronizationBarrier (); // Wait until MMC is idle do { Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_STATUS, TRUE, sizeof (MmcStatus), &MmcStatus); @@ -1588,16 +1591,23 @@ DwEmmcExecTrb ( if (EFI_ERROR (Status)) { return Status; } + ArmDataSynchronizationBarrier (); + ArmInstructionSynchronizationBarrier (); Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_CMD, FALSE, sizeof (Cmd), &Cmd); if (EFI_ERROR (Status)) { return Status; } + ArmDataSynchronizationBarrier (); + ArmInstructionSynchronizationBarrier (); ErrMask = DW_MMC_INT_EBE | DW_MMC_INT_HLE | DW_MMC_INT_RTO | DW_MMC_INT_RCRC | DW_MMC_INT_RE; ErrMask |= DW_MMC_INT_DCRC | DW_MMC_INT_DRT | DW_MMC_INT_SBE; do { - MicroSecondDelay (500); + Timeout = 10000; + if (--Timeout == 0) { + break; + } Status = DwMmcHcRwMmio (PciIo, Trb->Slot, DW_MMC_RINTSTS, TRUE, sizeof (IntStatus), &IntStatus); if (EFI_ERROR (Status)) { return Status; @@ -1605,9 +1615,12 @@ DwEmmcExecTrb ( if (IntStatus & ErrMask) { return EFI_DEVICE_ERROR; } - if (IntStatus & DW_MMC_INT_DTO) { // Transfer Done - break; + if (Trb->DataLen && ((IntStatus & DW_MMC_INT_DTO) == 0)) { + // Transfer Not Done + MicroSecondDelay (10); + continue; } + MicroSecondDelay (10); } while (!(IntStatus & DW_MMC_INT_CMD_DONE)); switch (Packet->SdMmcCmdBlk->ResponseType) { case SdMmcResponseTypeR1: @@ -1791,12 +1804,12 @@ DwSdExecTrb ( if (IntStatus & ErrMask) { return EFI_DEVICE_ERROR; } - if (Trb->DataLen && ((IntStatus & DW_MMC_INT_DTO) == 0)) { // Transfer Done + if (Trb->DataLen && ((IntStatus & DW_MMC_INT_DTO) == 0)) { + // Transfer not Done MicroSecondDelay (10); continue; - } else { - MicroSecondDelay (10); } + MicroSecondDelay (10); } while (!(IntStatus & DW_MMC_INT_CMD_DONE)); if (Packet->InTransferLength) { do { -- cgit v1.2.3 From 023b83ab597391b310d3e0a00d6f10a6289541c3 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Tue, 6 Mar 2018 17:32:55 +0800 Subject: Drivers/DwUsb3Dxe: fix uninitialized variable Signed-off-by: Haojian Zhuang --- Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.c b/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.c index c2fad30..408d744 100644 --- a/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.c +++ b/Drivers/Usb/DwUsb3Dxe/DwUsb3Dxe.c @@ -226,7 +226,7 @@ DwUsb3SetFifoSize ( IN UINT32 FifoNum ) { - UINT32 Reg; + UINT32 Reg = 0; if (Dir == FIFO_DIR_TX) { Reg = GTXFIFOSIZ (FifoNum); @@ -1219,7 +1219,7 @@ DwUsb3HandleEndPoint0 ( ) { usb3_pcd_ep_t *ep0 = &pcd->ep0; - usb3_dma_desc_t *desc; + usb3_dma_desc_t *desc = NULL; UINT32 byte_count, len; switch (pcd->ep0state) { -- cgit v1.2.3 From 65685632d801eb4183a3a84b7f3f4054465399a0 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 7 Mar 2018 22:04:37 +0800 Subject: Library/UsbSerialNumberLib: assign usb serialno Add the function to set specified usb serialno. Signed-off-by: Haojian Zhuang --- Include/Library/UsbSerialNumberLib.h | 6 ++++ Library/UsbSerialNumberLib/UsbSerialNumberLib.c | 39 +++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/Include/Library/UsbSerialNumberLib.h b/Include/Library/UsbSerialNumberLib.h index 3ae594b..0ab4cc7 100644 --- a/Include/Library/UsbSerialNumberLib.h +++ b/Include/Library/UsbSerialNumberLib.h @@ -36,6 +36,12 @@ GenerateUsbSN ( OUT CHAR16 *UnicodeSN ); +EFI_STATUS +AssignUsbSN ( + IN CHAR8 *AsciiCmd, + OUT CHAR16 *UnicodeSN + ); + EFI_STATUS LoadSNFromBlock ( IN EFI_HANDLE FlashHandle, diff --git a/Library/UsbSerialNumberLib/UsbSerialNumberLib.c b/Library/UsbSerialNumberLib/UsbSerialNumberLib.c index 2727d5c..550a973 100644 --- a/Library/UsbSerialNumberLib/UsbSerialNumberLib.c +++ b/Library/UsbSerialNumberLib/UsbSerialNumberLib.c @@ -28,6 +28,7 @@ #include +#define SERIAL_NUMBER_LEN 16 #define SERIAL_NUMBER_SIZE 17 #define RANDOM_MAX 0x7FFFFFFFFFFFFFFF @@ -104,6 +105,41 @@ GenerateUsbSN ( return EFI_SUCCESS; } +EFI_STATUS +AssignUsbSN ( + IN CHAR8 *AsciiCmd, + OUT CHAR16 *UnicodeSN + ) +{ + CHAR8 Data; + UINTN Index; + RANDOM_SERIAL_NUMBER RandomSN; + + if ((AsciiCmd == NULL) || (UnicodeSN == NULL)) { + return EFI_INVALID_PARAMETER; + } + for (Index = 0; Index < SERIAL_NUMBER_LEN; Index++) { + Data = *(AsciiCmd + Index); + if (((Data >= '0') && (Data <= '9')) || + ((Data >= 'A') && (Data <= 'F'))) { + continue; + } + // Always use with upper case + if ((Data >= 'a') && (Data <= 'f')) { + *(AsciiCmd + Index) = Data - 'a' + 'A'; + continue; + } + if (Data == '\0') { + break; + } + return EFI_INVALID_PARAMETER; + } + ZeroMem (&RandomSN, sizeof (RANDOM_SERIAL_NUMBER)); + AsciiStrToUnicodeStr (AsciiCmd, RandomSN.UnicodeSN); + StrCpyS (UnicodeSN, SERIAL_NUMBER_SIZE * sizeof (CHAR16), RandomSN.UnicodeSN); + return EFI_SUCCESS; +} + EFI_STATUS LoadSNFromBlock ( IN EFI_HANDLE FlashHandle, @@ -207,6 +243,7 @@ StoreSNToBlock ( CHAR16 UnicodeStr[SERIAL_NUMBER_SIZE]; if (UnicodeSN == NULL) { +DEBUG ((DEBUG_ERROR, "#%a, %d\n", __func__, __LINE__)); return EFI_INVALID_PARAMETER; } Status = gBS->OpenProtocol ( @@ -236,10 +273,12 @@ StoreSNToBlock ( ZeroMem (UnicodeStr, SERIAL_NUMBER_SIZE * sizeof (CHAR16)); UnicodeSPrint (UnicodeStr, SERIAL_NUMBER_SIZE * sizeof (CHAR16), L"%lx", RandomSN->Data); if (StrLen (RandomSN->UnicodeSN) != StrLen (UnicodeStr)) { +DEBUG ((DEBUG_ERROR, "#%a, %d, strlen:%d, %d\n", __func__, __LINE__, StrLen (RandomSN->UnicodeSN), StrLen (UnicodeStr))); Status = EFI_INVALID_PARAMETER; goto Exit; } if (StrnCmp (RandomSN->UnicodeSN, UnicodeStr, StrLen (UnicodeStr)) != 0) { +DEBUG ((DEBUG_ERROR, "#%a, %d, %s, %s\n", __func__, __LINE__, RandomSN->UnicodeSN, UnicodeStr)); Status = EFI_INVALID_PARAMETER; goto Exit; } -- cgit v1.2.3 From 43e836468cf761cbc7cf0d0d24cef20c3871243b Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 7 Mar 2018 22:05:38 +0800 Subject: Platforms/HiKey: set specified serialno Signed-off-by: Haojian Zhuang --- .../HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c | 27 ++++++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c b/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c index a62c094..ee45b99 100644 --- a/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c +++ b/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c @@ -562,15 +562,32 @@ HiKeyFastbootPlatformOemCommand ( { EFI_STATUS Status; CHAR16 UnicodeSN[SERIAL_NUMBER_SIZE]; + UINTN Size; + Size = AsciiStrLen ("serialno"); if (AsciiStrCmp (Command, "Demonstrate") == 0) { DEBUG ((DEBUG_ERROR, "ARM OEM Fastboot command 'Demonstrate' received.\n")); return EFI_SUCCESS; - } else if (AsciiStrCmp (Command, "serialno") == 0) { - Status = GenerateUsbSN (UnicodeSN); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Failed to generate USB Serial Number.\n")); - return Status; + } else if (AsciiStrnCmp (Command, "serialno", Size) == 0) { + while (*(Command + Size) == ' ') { + Size++; + } + if (AsciiStrnCmp (Command + Size, "set", AsciiStrLen ("set")) == 0) { + Size += AsciiStrLen ("set"); + while (*(Command + Size) == ' ') { + Size++; + } + Status = AssignUsbSN (Command + Size, UnicodeSN); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to set USB Serial Number.\n")); + return Status; + } + } else { + Status = GenerateUsbSN (UnicodeSN); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to generate USB Serial Number.\n")); + return Status; + } } Status = StoreSNToBlock (mFlashHandle, SERIAL_NUMBER_LBA, UnicodeSN); return Status; -- cgit v1.2.3 From d3cd62f1dc9d7bb9db41d04fa604992843fc0839 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 7 Mar 2018 22:06:18 +0800 Subject: Platforms/HiKey960: set specified serialno Signed-off-by: Haojian Zhuang --- .../HiKey960FastbootDxe/HiKey960FastbootDxe.c | 27 ++++++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/HiKey960FastbootDxe.c b/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/HiKey960FastbootDxe.c index c87040d..355119c 100644 --- a/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/HiKey960FastbootDxe.c +++ b/Platforms/Hisilicon/HiKey960/HiKey960FastbootDxe/HiKey960FastbootDxe.c @@ -612,15 +612,32 @@ HiKey960FastbootPlatformOemCommand ( { EFI_STATUS Status; CHAR16 UnicodeSN[SERIAL_NUMBER_SIZE]; + UINTN Size; + Size = AsciiStrLen ("serialno"); if (AsciiStrCmp (Command, "Demonstrate") == 0) { DEBUG ((DEBUG_ERROR, "ARM OEM Fastboot command 'Demonstrate' received.\n")); return EFI_SUCCESS; - } else if (AsciiStrCmp (Command, "serialno") == 0) { - Status = GenerateUsbSN (UnicodeSN); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Failed to generate USB Serial Number.\n")); - return Status; + } else if (AsciiStrnCmp (Command, "serialno", Size) == 0) { + while (*(Command + Size) == ' ') { + Size++; + } + if (AsciiStrnCmp (Command + Size, "set", AsciiStrLen ("set")) == 0) { + Size += AsciiStrLen ("set"); + while (*(Command + Size) == ' ') { + Size++; + } + Status = AssignUsbSN (Command + Size, UnicodeSN); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to set USB Serial Number.\n")); + return Status; + } + } else { + Status = GenerateUsbSN (UnicodeSN); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to generate USB Serial Number.\n")); + return Status; + } } Status = StoreSNToBlock (mFlashHandle, SERIAL_NUMBER_LBA, UnicodeSN); return Status; -- cgit v1.2.3 From 42a98dec580d7f01ab8665a84bcb8659419622e5 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 21 Mar 2018 12:28:08 +0800 Subject: Platforms/HiKey960: fix product string Fix product string from "Linaro" to "HiKey960". Signed-off-by: Haojian Zhuang --- Platforms/Hisilicon/HiKey960/HiKey960.dsc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platforms/Hisilicon/HiKey960/HiKey960.dsc b/Platforms/Hisilicon/HiKey960/HiKey960.dsc index dd9a40e..149d333 100644 --- a/Platforms/Hisilicon/HiKey960/HiKey960.dsc +++ b/Platforms/Hisilicon/HiKey960/HiKey960.dsc @@ -282,7 +282,7 @@ gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Linaro" + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"HiKey960" gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha" gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"HiKey960" -- cgit v1.2.3 From f860b1dc59ef431e55f38cab41cc9b79de77b915 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Mon, 26 Mar 2018 12:52:06 +0800 Subject: Drivers/DwUfsHcDxe: flush data in UfsHcFlush Signed-off-by: Haojian Zhuang --- Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c index 3fac2d3..4334269 100644 --- a/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c +++ b/Drivers/Block/DwUfsHcDxe/DwUfsHcDxe.c @@ -310,6 +310,8 @@ UfsHcFlush ( IN EDKII_UFS_HOST_CONTROLLER_PROTOCOL *This ) { + ArmInstructionSynchronizationBarrier (); + ArmDataSynchronizationBarrier (); return EFI_SUCCESS; } -- cgit v1.2.3 From 18e8dfa129dae88acafc3a0a641589d0f16a7f82 Mon Sep 17 00:00:00 2001 From: Dmitry Shmidt Date: Tue, 27 Mar 2018 15:19:05 -0700 Subject: Platforms/HiKey960: Fix product string to 'hikey960' Change-Id: I3ee3276c4a465a1f4394021bd4979421f63571e7 Signed-off-by: Dmitry Shmidt --- Platforms/Hisilicon/HiKey960/HiKey960.dsc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platforms/Hisilicon/HiKey960/HiKey960.dsc b/Platforms/Hisilicon/HiKey960/HiKey960.dsc index 149d333..6d29dec 100644 --- a/Platforms/Hisilicon/HiKey960/HiKey960.dsc +++ b/Platforms/Hisilicon/HiKey960/HiKey960.dsc @@ -282,7 +282,7 @@ gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"HiKey960" + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"hikey960" gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha" gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"HiKey960" -- cgit v1.2.3 From f0e4df7fd480059f5b9e1b4c80efaeaf85325c5f Mon Sep 17 00:00:00 2001 From: Dmitry Shmidt Date: Tue, 27 Mar 2018 15:10:10 -0700 Subject: Platforms/hikey: Add vendor partition type support Change-Id: I0e2c9bf09b8b174987ac524f9755cb26724f79f9 Signed-off-by: Dmitry Shmidt --- Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c b/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c index ee45b99..865258b 100644 --- a/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c +++ b/Platforms/Hisilicon/HiKey/HiKeyFastbootDxe/HiKeyFastbootDxe.c @@ -540,7 +540,8 @@ HiKeyFastbootPlatformGetVar ( } else if ( !AsciiStrnCmp (Name, "partition-type", 14)) { DEBUG ((DEBUG_ERROR, "Fastboot platform: check for partition-type:%a\n", (Name + 15))); if ( !AsciiStrnCmp ( (Name + 15) , "system", 6) || !AsciiStrnCmp ( (Name + 15) , "userdata", 8) - || !AsciiStrnCmp ( (Name + 15) , "cache", 5)) { + || !AsciiStrnCmp ( (Name + 15) , "cache", 5) + || !AsciiStrnCmp ( (Name + 15) , "vendor", 6)) { AsciiStrCpy (Value, "ext4"); } else { AsciiStrCpy (Value, "raw"); -- cgit v1.2.3